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研究生： 錢信達
Chien, Hsin-Ta
論文名稱： 一個應用於神經網路之全類比式記憶體內運算加速器
A Fully Analog Computing-in-Memory Accelerator for Neural Network
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2023
畢業學年度： 111
語文別： 英文
論文頁數： 139
中文關鍵詞： 記憶體內運算 、類比人工智慧加速器 、神經網路 、電荷重新分佈 、類比運算 、靜態隨機存取記憶體
外文關鍵詞： computing-in-memory (CIM), analog ai accelerator, neural network (NN), charge redistribution, fully analog computation, static random access memory (SRAM)
相關次數： 點閱：132  下載：7 
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    • 本論文提出一個應用於神經網路以全類比式處理之記憶體內運算人工智慧加速器。本論文提出全新架構以進行全類比式的運算，捨棄了記憶體內運算巨集常用的類比數位轉換器、數位類比轉換器以及存儲上述所產生之數位碼的暫存器，將以上電路的功能整合至切換式電容積分器。其中靜態隨機存取記憶體採用了九顆電晶體，其可直接讀取權重以實現運算，並可在運算時避免誤寫入資料。此外，本論文提出了三個技巧：第一個技巧為電容式類比接收單元，輔以電荷重新分佈來進行乘加運算，此方法比常見的電流充放電方式具有較佳的線性度，且可直接接收類比電壓進行運算，不需要數位類比轉換器；第二個技巧為基於電荷共享的類比累進加法電路，與傳統數位式存儲電路與加法器相較，具有低功耗的優點；第三個技巧為內建二補數產生技術的切換式電容積分器，有利於增加運算速度、降低功耗。
    本設計以台積電180 nm CMOS標準1P6M製程實作測試晶片，整體晶片面積為25 mm2，核心電路占整體的90%。測試結果顯示本晶片在MNIST的Top-1準確率可達88%。在輸入電壓1.8伏特及2.044μs的圖片判斷速度下，記憶體內運算電路的能源效率為457.0 TOPS/W，神經網路運算系統的能源效率為1.88 TOPS/W；在輸入電壓1.6伏特下，而記憶體內運算電路的能源效率為706.3 TOPS/W，神經網路運算系統的能源效率為3.03 TOPS/W。

    This thesis presents a fully analog processing computing-in-memory (CIM) prototype chip for neural network. This chip proposes a new architecture for fully analog computing, abandoning the analog-to-digital converters, digital-to-analog converters and registers that store the generated digital codes commonly used in other CIM macros, and integrating the above-mentioned functions into a switched-capacitor integrator. The CIM macro adopts 9T static random access memory (SRAM) cell, in which the internal computing read port can directly read the weight in order to realize the MAC computation. In addition, this thesis proposes three techniques: the first technique is a capacitive analog receiver unit, and it can implement the multiplication and accumulation by charge redistribution. This method has better linearity than the current charging and discharging methods, and can directly receive analog voltages to perform computations without the need for a digital-to-analog converter. The second technique is an analog accumulative circuit based on charge sharing operation, which has the advantage of reducing power consumption compared with traditional digital storage circuits and adders. The third technique is a switched-capacitor integrator with built-in two's complement generation technique, which is beneficial to increase computing speed and reduce power consumption.
    The proof-of-concept prototype was fabricated in TSMC's 180 nm CMOS standard 1P6M technology. The chip area is 25 mm2, and the core circuit accounts for 90%. The chip achieves 88% of Top-1 accuracy with MNIST. The measurement results show that at 1.8V input voltage and 2.044μs of inference speed per image, the energy efficiency of the CIM-macro is 457.0 TOPS/W, and the energy efficiency of neural-network-computing system is 1.88 TOPS/W; at 1.6V input voltage, the energy efficiency of the CIM-macro is 706.3 TOPS/W, and the energy efficiency of neural-network-computing system is 3.03 TOPS/W.

    摘 要 I Abstract III List of Tables IX List of Figures X Chapter 1 Introduction 1 1.1 Background and Motivation of Accelerator 1 1.2 Memory Centric Computation 3 1.3 Thesis Organization 5 Chapter 2 Overview of Neural Networks and Data Management 7 2.1 Introduction of Neural Networks 8 2.2 Basics of Convolutional Neural Network 12 2.2.1 Convolutional Neural Networks 12 2.2.2 Fully Connected Neural Networks 13 2.2.3 Non-Linear Activation Function 13 2.2.4 Pooling Function 14 2.2.5 Normalization Function 15 2.3 Quantization of Neural Networks 16 2.3.1 Linear Quantization 17 2.3.2 Non-Linear Quantization 18 2.3.3 Quantization-Aware Training 19 2.4 Introduction of Data Movement 20 2.4.1 Dataflow 20 2.4.2 Data Reuse 23 Chapter 3 Fundamental of Conventional Computing-in-Memory 26 3.1 Introduction to Computing-in-Memory 28 3.1.1 Concept of Computing-in-Memory 28 3.1.2 Dataflow and Structure of Computing-in-Memory 30 3.2 Digital-to-Analog Conversion 31 3.2.1 Fundamental of DAC 32 3.2.2 Static Specifications of DAC 34 3.2.3 Output types of DAC in CIM 37 3.3 Mixed-Signal Computation with SRAM 38 3.3.1 Classic 6T SRAM Bit-cell 38 3.3.2 Current-Based Multiplication and Accumulation 42 3.3.3 Charge-Based Multiplication and Accumulation 47 3.4 Mixed-Signal Computation with RRAM 49 3.4.1 Classic RRAM Bit-cell 49 3.4.2 Current-Based Multiplication and Accumulation 50 3.5 Analog-to-Digital Conversion 54 3.5.1 The Concept and Operation of SAR ADC 55 3.5.2 Quantization Error 58 3.5.3 Static Specifications of ADC 59 Chapter 4 Proposed Architecture: A Fully Analog Processing Computing-in-Memory AI Accelerator for Neural Network 62 4.1 Introduction 62 4.2 Proposed Architecture 63 4.3 Proposed Techniques 68 4.3.1 Analog Computing Unit 68 4.3.2 Analog Domino: Shift and Accumulation Method 70 4.3.3 Shadow 2’s Compliment Generation into the Integrator 74 4.4 Circuit Implementation 75 4.4.1 Peripheral Circuits of SRAM 75 4.4.2 Switched-Capacitor-Based Integrator 78 4.4.3 Bias Circuits 89 4.4.4 Dynamic Comparator 91 4.4.5 Capacitors on SRAM Cell for Computing 94 Chapter 5 Simulation and Measurement Results 97 5.1 Layout and Chip Floor Plan 97 5.2 Simulation Results 102 5.3 Die Micrograph and Measurement Setup 105 5.4 Measurement Results 113 Chapter 6 Conclusion and Future Works 130 Bibliography 132

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