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研究生：	羅中冠 Luo, Jung-Guan
論文名稱：	相容於OCP之可規劃性匯流排架構設計 OCP-Compliant Configurable Bus Architecture Design
指導教授：	謝明得 Shieh, Ming-Der
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2009
畢業學年度：	97
語文別：	中文
論文頁數：	91
中文關鍵詞：	匯流排架構設計、可規劃性、開放核心協定 (OCP)
外文關鍵詞：	bus architecture design, configurable, Open Core Protocol (OCP)
相關次數：	點閱：109 下載：6
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在單晶片系統(SoC)的發展中，系統設計不僅朝向多功能整合發展，也針對產品上市時間有了越來越嚴苛的要求。然而在眾多設計應用之下，現今被廣泛應用的 AMBA 2.0 AHB 或是其他不同規格匯流排所能提供之傳輸效能已逐漸不符需求，使得匯流排存取之過程常造成單晶片系統中的瓶頸。為此我們採用由OCP-IP 所規劃之新一代晶片間傳輸介面，開放核心傳輸協定(Open Core Protocol)，實作出與其相容之模擬環境與硬體架構。
本論文依據系統中常見的不同應用，將 OCP 所制定的諸多功能分為五種系統設定(Profile)，使得系統整合者能夠選擇最適合之系統傳輸架構以節省硬體面積。其中為了提供較典型連結共享式匯流排(Share-link Bus)或稱為集中仲裁式匯流排(Centralized Arbitration Bus)有更大的傳輸量，我們也設計了縱橫式交換(Crossbar)連接架構，並可允許各元件進行點對點(Point-to-Point)的傳輸。此外，對於矽智財(IP)與匯流排間的可連接性(Interoperability)問題，我們對於傳輸介面增加了對應的插槽(Socket)模組。經由插槽模組對傳輸訊號的處理，IP 設計者只
需定義本身需求之部分 OCP 訊號，即可透過插槽模組與系統溝通。因此可將設計 IP 外覆模組(Wrapper)之複雜度轉移至插槽模組中，以期能增加系統上連接元件之彈性並縮短系統整合時程。
藉由 Synopsys 所提供之 VIP軟體，我們進行了系統驗證以及分析不同介面設定下所能提供的傳輸效能。根據 VIP 所提供的模擬結果，所提出之匯流排架構在高傳輸量之系統設定下與相容 AHB之系統設定相較，能減少至少 46% 的傳輸時間。本論文所提出之硬體架構以Verilog 硬體描述語言實現，並以 0.13 微米CMOS 製程進行合成，電路最高操作速度可達 333 MHz。

The trend of integrating more and more components and functionalities in system-on-a-chip (SoC) design has made it a very challenging task. The need of fitting the time-to-market of a product also imposes strict requirements on system development. It is not surprising today that a highly integrated commercial product can support various types of applications such as multimedia and wireless communication and so on. This implies that the commonly used bus protocols like AMBA 2.0 AHB may not be suitable for applications demanding high data bandwidth, and may become a bottleneck of system integration. The Open Core Protocol (OCP) is a new specification of bus transaction interface for facilitating the system integration. This thesis explores various OCP-compliant configurable bus architecture designs which are verified via an CP-compliant simulation environment.
To comply with different applications, we classify the features drawn in OCP into five architecture profiles. Users can choose the most appropriate one for their applications to save hardware requirements. In addition to developing building blocks for the typical share-link bus, we also consider the crossbar structure for obtaining a higher transmission bandwidth and supporting point-to-point communication between IPs. For the interoperability issues, we introduce the IP-specific socket module in the bus interface so that IP providers can define their own interface configuration and only focus on the necessary OCP signals. By moving all the details of hooking up the bus into the socket design, it becomes much easier and flexible for IP integration.
The proposed hardware architectures have been successfully implemented with Verilog HDL and synthesized using 0.13 贡m CMOS technology. Using Synopsys VIP tools, we built the simulation environment to verify our development and analyzed the resulting performance for different configurations. Experimental results show that the proposed high-performance bus architecture profile can reduce the transmission time by 46% as compared to the AHB-compliant bus architecture profile, and can operate in 333MHz.

第一章  研究緒論....................................................................1 
1. 研究背景.......................................................................1 
2. 研究動機.......................................................................3 
3. 論文架構.......................................................................4 
第二章 OCP傳輸協定概述..............................................................6 
1. OCP之操作原理..................................................................6 
1.1. 點對點傳輸介面...............................................................6 
1.2. 匯流排獨立性.................................................................6 
1.3. 傳遞管線化...................................................................7 
1.4. 可選擇式回應機制.............................................................9 
1.5.  Burst類型傳輸...............................................................10 
1.6. 多重未完成傳輸...............................................................11 
1.7. 標籤化傳輸...................................................................12 
1.8. 多執行緒傳輸.................................................................13 
2. 相關研究.......................................................................15 
第三章  系統規格....................................................................16 
1. 需求分析.......................................................................16 
2. 系統設定.......................................................................19 
2.1. 周邊設定. ...................................................................20 
2.2. 基礎設定. ...................................................................22 
2.2.1.  元件端介面設定............................................................23 
2.2.2.  提出之選擇性功能..........................................................25 
2.3. SRMD設定.....................................................................27 
2.3.1.  元件端介面設定............................................................28 
2.3.2.  提出之選擇性功能..........................................................29 
2.4. 傳輸標籤設定.................................................................32 
2.4.1.  元件端介面設定............................................................32 
2.4.2.  提出之選擇性功能..........................................................34 
2.5. 多執行緒設定.................................................................36 
2.5.1.  層級 1 –基本效能層級......................................................37 
2.5.1.1. 元件端介面設定...........................................................37 
2.5.1.2. 提出之選擇性功能.........................................................38 
2.5.2.  層級 2 –高效能層級........................................................40 
2.5.2.1. 元件端介面設定...........................................................40 
2.5.2.2. 提出之選擇性功能.........................................................42
第四章  架構設計與硬體實現..........................................................44 
1. 周邊設定.......................................................................44 
1.1. 發送階段資料流程.............................................................45 
1.1.1.  發送階段仲裁器............................................................45 
1.1.2.  解碼器....................................................................46 
1.2. 回應階段資料流程.............................................................46 
2. 基礎設定.......................................................................47 
2.1. Slave Socket模組.............................................................48 
2.2. 系統連接模組.................................................................50 
2.3. Master Socket模組............................................................52 
3. SRMD設定.......................................................................54 
3.1. Slave Socket模組.............................................................55 
3.2. 系統連接模組.................................................................57 
4. 傳輸標籤設定...................................................................58 
4.1. Slave Socket模組.............................................................58 
4.2. 系統連接模組.................................................................60 
5. 多執行緒設定...................................................................60 
5.1. 層級 1 – 基本效能層級........................................................61 
5.2. 層級 2 – 高效能層級..........................................................62 
5.2.1. Slave Socket模組...........................................................63 
5.2.2.  系統連接模組..............................................................65 
5.2.3. Master Socket模組..........................................................65 
第五章 OCP之介面可連接性討論........................................................67 
1. 訊號不匹配之分類...............................................................68 
2. 架構設計.......................................................................71 
2.1. Slave Socket模組.............................................................71 
2.2. Master Socket模組............................................................72 
第六章  系統驗證....................................................................73 
1. 系統驗證環境...................................................................73 
2. 驗證計畫.......................................................................74 
2.1. 驗證流程. ...................................................................75 
2.2. 功能性涵蓋率.................................................................76 
第七章  實驗結果與分析..............................................................79 
1. 合成結果.......................................................................79 
2. 系統效能分析...................................................................81 
2.1. 傳輸延遲. ...................................................................81 
2.2. 傳輸效能. ...................................................................82 
2.3. 與相關研究之數據比較.........................................................85 
第八章  結論與未來計畫..............................................................88 
1. 結論...........................................................................88 
2. 未來計畫.......................................................................89
                                    

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校內：2014-08-19公開
校外：2014-08-19公開

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