本論文實現一寬頻高解析之連續時間三角積分調變器，此調變器包含一個五階前饋式架構迴圈濾波器、一個具參考資料加權平均機制之五位元量化器以及五位元回授電源式數位類比轉換器。迴圈濾波器使用低增益高速反向器式放大器搭配增益提升技術以較佳的功耗效率達到高速需求。此外，相較於傳統用在數位類比轉換器誤差校正的資料加權平均技術，參考資料加權平均技術不但可以同時處理數位類比轉換器的電流誤差以及比較器的偏移誤差外，還能避免資料加權平均技術譯碼器在回授路徑上產生延遲。
本設計案實現於TSMC 28nm 互補型金氧半導體製程，操作在5GHz速度下以超取樣率5達到500MHz頻寬。根據驗證結果顯示在1V電源電壓、300mW功耗情況下，可達到65dB最大信噪失真比以及71 dB動態範圍，ADC效能指標FOM為202 fJ/conversion-step。

A wide-bandwidth high-resolution continuous-time delta-sigma modulator (CTΔΣM) is implemented in this paper. The modulator comprises a fifth-order loop filter with feedforward architecture, a 5-bit quantizer incorporating reference data-weighted-averaging (DWA) scheme, and 5-bit feedback current steering digital-to-analog converters (DACs). Low-gain high-speed inverter-based amplifier with gain enhancement technique are used in the loop filter to meet the high-speed requirement in a power efficient fashion. Furthermore, compared to traditional DWA for DAC mismatch correction, the reference DWA not only handles the DAC mismatch error and comparator offset error at the same time but also eliminates the DWA decoder delay in the feedback path.
This work is implemented in TSMC 28 nm CMOS process which is clocked at 5 GHz with an OSR of 5, providing a signal bandwidth of 500 MHz. The pre-simulation results show that the modulator consumes 300mW of power from 1 V supply and achieves 65 dB peak SNDR and 71 dB dynamic range (DR). The Walden Figure of Merit (FoM) is 202 fJ/conversion-step.

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