成功大學博碩士論文系統

簡易檢索 / 詳目顯示

回結果列表

研究生：	歐信宏 Ou, Hsin-Hung
論文名稱：	運用於管線式類比數位轉換器中以切換運算放大器架構為基礎之低電壓低功率電路設計技術 Circuit Techniques for Low-voltage Low-Power Pipelined A/D Converters Based on Switched-Opamp Architecture
指導教授：	張順志 Chang, Soon-Jyh 劉濱達 Liu, Bin-Da
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2008
畢業學年度：	96
語文別：	英文
論文頁數：	83
中文關鍵詞：	低電壓、低功率、管線式類比數位轉換器、切換運算放大器技術
外文關鍵詞：	switched-opamp, pipelined ADC, low-voltage, low-power
相關次數：	點閱：166 下載：14
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

本論文主要提出了三個以切換運算放大器架構為基礎的電路技術來達成低電壓，低功率且具高速應用潛力之管線式類比數位轉換器設計。
首先本論文提出一個可將切換運算放大器架構之缺點轉化為優點的逆翻轉式取樣保持電路。傳統上以切換運算放大器架構設計的取樣保持電路，其迴授因子為二分之一。本論文中所提出的逆翻轉式取樣保持電路之迴授因子為一，因此可操作在較高的取樣頻率，且具有較低的雜訊。其次，本論文改良運算放大器共享技術，透過一個具有雙輸出級的運算放大器，使運算放大器可在以切換運算放大器架構為基礎之管線式類比數位轉換器中被共享，因此可以大幅節省功率消耗。最後，本論文將無負載技術應用在我們所提出的運算放大器共享架構上，以達成更低的功率與更高的運算速度。
基於以上所提出的電路技術，本論文用三個設計實例來驗證：
(1)一個0.8伏特 3.5毫瓦 250百萬取樣/秒的逆翻轉式取樣保持電路：利用本論文提出的逆翻轉式取樣保持電路架構，再配合對時脈偏差不敏感的雙取樣電路，整體的取樣速度可以大幅提昇。在此設計中，我們使用了一個具有雙輸入差動對與雙輸出級的運算放大器。此運算放大器具有消去記憶效應與提高切換速度的優點。經利用0.13-um CMOS製程的模擬結果顯示此取樣保持電路在0.8伏特電源電壓以及250 百萬取樣/秒下僅有–67.3 dB 的總諧波失真。功率消耗為3.5毫瓦，FOM為7.4 fJ/step。
(2)一個0.8伏特、9位元、10百萬取樣/秒的管線式類比數位轉換器：運用本論文中提出的運算放大器共享架構，我們設計了一個操作在0.8伏特電壓下的9位元管線式類比數位轉換器。經利用0.18-um CMOS製程的模擬結果顯示其FOM可達到0.71 pJ/step。
(3) 一個0.8伏特、9位元、20 百萬取樣/秒的管線式類比數位轉換器：本設計運用了論文中所提出的電路架構，結合了運算放大器共享技術與無負載式結構。經利用0.18-um CMOS製程的模擬結果，顯示其功率消耗為4.5毫瓦，FOM可達到0.58 pJ-Volts/step。
綜上所述，在本論文中我們分析了切換運算放大器架構的優缺點，針對其缺點加以改良，並提出相關的低電壓低功率設計技術。這些技術可應用於實現低壓低功率之管線式類比數位轉換器。

In this dissertation, three novel circuit techniques based on switched-opamp (SO) architecture are proposed to facilitate the design of low-voltage, low-power pipelined analog-to-digital converters with high-speed potential. First, an inverse-flip-around sample-and-hold (IFA S/H) which takes advantage of the drawbacks in SO architecture is proposed. Conventional SO-based S/H has a feedback factor of 1/2. The feedback factor of the proposed IFA S/H is 1, and therefore can be operated at a higher sampling rate with reduced noise contribution. Second, opamp-sharing is incorporated into SO architecture by employing a dual-output opamp, leading to great saving in the overall power consumption of the pipelined ADC. Finally, loading-free architecture is merged with opamp-sharing technique to provide more power reduction and higher speed potential. Based on the aforementioned techniques, three design examples are given to validate the proposed ideas, including:
(i) A 0.8-V 3.5 mW 250 MS/s IFA S/H: the proposed SO-based IFA S/H architecture which maximizes the feedback factor is employed in this S/H. A skew-insensitive double-sampling mechanism is presented to increase the throughput by a factor of two while eliminating the timing mismatch associated with double-sampling circuits. Furthermore, a dual-input dual-output opamp is proposed to incorporate double-sampling into the switched-opamp based S/H. This opamp also removes the memory effect in double-sampling circuitry and features fast turn-on time to improve the speed performance in switched-opamp circuits. Simulation results using a 0.13-um CMOS process model demonstrates the proposed S/H circuit has a total-harmonic-distortion of –67.3 dB up to 250 MSample/s and a 0.8 Vpp input range at 0.8 V supply. The power consumption is 3.5 mW and the figure-of-merit is only 7.4 fJ/step.
(ii) A 0.8-V 9-bit 10 MS/s pipelined ADC: Opamp-sharing is merged into switched-opamp structure with a proposed dual-output opamp configuration. A 0.8-V, 9-bit, 10-Msample/s pipelined ADC is designed to verify the proposed circuit. Simulation results using a 0.18-um CMOS 1P6M process demonstrate the figure-of-merit of this pipelined ADC is only 0.71 pJ/step.
(iii) A 0.8-V 9-bit 20 MS/s pipelined ADC: A novel circuit architecture which merges opamp-sharing with loading-free structure is proposed. Such mechanism effectively reduces the number of opamps as well as the capacitive loading. Simulation results using a 0.18-um CMOS 1P6M process demonstrate the power consumption of this pipelined ADC is 4.5 mW which amounts to a figure-of-merit of 0.58 pJ-Volts/step.
As a consequence, the pros and cons of SO architecture and the proposed SO-based circuit techniques are analyzed, designed, and verified in this dissertation. These techniques can be properly manipulated for achieving a low-voltage power-efficient pipelined ADC.

ABSTRACT...........................................................................................................................i
ACKNOWLEDGMENT......................................................................................................v
List of Tables.......................................................................................................................xii
List of Figures....................................................................................................................xiii
CHAPTER 1 Introduction...................................................................................................1
    1.1 Background and Motivation.....................................................................................1
    1.2 Organization of the Dissertation...............................................................................3

CHAPTER 2 Design Considerations and Techniques for Low-Voltage 
Pipelined ADC..............................................................................................4
    2.1 Considerations for Low-Voltage Analog Circuit Design.........................................4
    2.2 Switched-Opamp Technique....................................................................................6
2.2.1 Operation Principle............................................................................................6
2.2.2 Imperfections of SO Architecture......................................................................9
    2.3 Pipelined ADC........................................................................................................11
    2.4 Summary................................................................................................................16

CHAPTER 3 Proposed Switched-Opamp Based Circuit Techniques for 
Pipelined ADC............................................................................................17
    3.1 Inverse-Flip-Around Sample-and-Hold.................................................................18
3.1.1 Fundamentals of Sample-and-Hold..............................................................18
3.1.2 Low-Voltage CMOS Sample-and-Hold Architecture...................................21
   3.1.2.1 Miller-Capacitance-Based S/H.............................................................22
3.1.2.2 Flip-Around S/H...................................................................................23
3.1.2.3 Low-Voltage S/H Using Shifted Input/Output 
Common-Mode Level...........................................................................24
3.1.2.4 SO-based Charge-redistribution S/H....................................................25
3.1.3 Proposed IFA S/H..........................................................................................26
    3.2 Opamp-Sharing in Switched-Opamp Architecture.................................................27
3.2.1 Opamp-Sharing.............................................................................................28
       3.2.2 Opamp-Sharing in Switched-Opamp Configuration.....................................29
    3.3 Loading-free + Opamp-Sharing + Switched-Opamp.............................................30
3.3.1 Loading-Free Architecture............................................................................30
       3.3.2 Proposed Opamp-Shared Loading-Free Architecture...................................33
    3.4 Summary................................................................................................................33

CHAPTER 4 Design Example I: A 0.8-V 250-MS/s 3.5-mW Inverse-Flip-
Around S/H.................................................................................................35
    4.1 Double-Sampled Inverse-Flip-Around Sample-and-Hold.....................................35
       4.1.1 Low-Voltage S/H Design Issues....................................................................35
       4.1.2 Inverse-Flip-Around S/H Architecture..........................................................37
       4.1.3 Skew-Insensitive Double-Sampling IFA S/H................................................40
    4.2 Opamp Design........................................................................................................41
    4.3 Simulation Results..................................................................................................44
    4.4 Summary................................................................................................................46
    
CHAPTER 5 Design Example II: A 0.8-V, 9-bit, 10-MS/s Pipelined ADC....................48
    5.1 ADC Architecture...................................................................................................48
    5.2 Merging of Opamp-Sharing and Switched-Opamp Techniques.............................49
    5.3 Inverse-Flip-Around (IFA) Sample-and-Hold........................................................52
    5.4 Power Analysis.......................................................................................................52
    5.5 Circuit Design.........................................................................................................53
       5.5.1 Opamp Design...............................................................................................53
       5.5.2 Low-Voltage Comparator Design..................................................................56
    5.6 Simulation Results..................................................................................................57
    5.7 Measurement Results..............................................................................................61
    5.8 Summary.................................................................................................................63

CHAPTER 6 Design Example III: A 0.8-V, 9-bit, 20-MS/s Pipelined ADC 
Using Loading-Free Architecture...............................................................64
    6.1 Opamp-shared Loading-free Architecture..............................................................64
6.1.1 ADC Architecture............................................................................................64
6.1.2 Opamp-sharing in Loading-Free Architecture................................................65
    6.2 Circuit Design.........................................................................................................67
    6.3 Simulation Results..................................................................................................68
    6.4 Summary.................................................................................................................70
CHAPTER 7 Conclusions and Future Work...................................................................71
7.1 Conclusions............................................................................................................71
7.2 Future Work............................................................................................................72
References...........................................................................................................................74
Publication List...................................................................................................................81
                                    

[1] S. H. Lewis and P. R. Gray, “A pipelined 5-Msample/s 9-bit analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. SC-22, no. 6, pp. 954-961, Dec. 1987.
[2] B. S. Song, M. F. Tompsett, and K. R. Lakshmikumar, “A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converter,” IEEE J. Solid-State Circuits, vol. 24, no. 6, pp. 1324-1333, Dec. 1988.
[3] S. Sutarja and P. R. Gray, “A pipelined 13-bit, 250-ks/s, 5-V analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 1316-1323, Dec. 1988.
[4] Y.-M. Lin, B. Kim, and P. R. Gray, “A 13-b, 2.5-MHz self-calibrated pipelined A/D converter in 3-um CMOS,” IEEE J. Solid-State Circuits, vol. 26, no. 4, pp. 628–636, Apr. 1991.
[5] S. H. Lewis, “Optimizing the stage resolution in pipelined, multistage, analog-to-digital converters for video-rate applications,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process. vol. 39, no. 8, pp. 516-523, Aug. 1992.
[6] S. H. Lewis, H. S. Fetterman, G. F. Gross, Jr., R. Ramachandran, and T. R. Viswanathan, “A 10-b 20-Msample/s analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 27, no. 3, pp. 351-358, Mar. 1992.
[7] A. N. Karanicolas, H.-S. Lee, and K. L. Bacrania, “A 15-b 1-Msample/s digitally self-calibrated pipeline ADC,” IEEE J. Solid-State Circuits, vol. 28, no. 12, pp. 1207–1215, Dec. 1993.
[8] F. Maloberti, F. Francesconi, P. Malcovati, and O. Nys, “Design consideration on low-voltage low-power data converters,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl. vol. 42, no. 11, pp. 853–863, Nov. 1995.
[9] T. B. Cho, and P. R. Gray, “A 10-b 20-Msample/s 35 mW Pipeline A/D converter,” IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 166-172, Mar 1995.
[10] W. Song, H. Choi, S. Kwak, and B. Song, “A 10-b 20-Msample/s low power CMOS ADC,” IEEE J. Solid-State Circuits, vol. 30, no. 5, pp. 514-521, May 1995.
[11] D. W. Cline, and P. R. Gray, “A power optimized 13-b 5 Msample/s pipelined analog-to-digital converter in 1.2 um CMOS,” IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 294-303, Mar. 1996.
[12] J. Goes, J. C. Vital, and J. E. Franca, “Systematic design for optimization of high-speed self-calibrated pipelined A/D converters,” IEEE Trans. Circuits Syst. II, Analog and Digital Signal Processing, vol. 45, no. 12, pp.1513-1526, Dec. 1998.
[13] I. E. Opris, L. D. Lewicki, and B. C. Wong, “A single-ended 12-bit 20 Msample/s self-calibrating pipeline A/D converter,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1898-1903, Dec. 1998.
[14] D. Y. Chang and S. H. Lee, “Design techniques for a low-power low-cost CMOS A/D converter,” IEEE J. Solid-State Circuits, vol. 33, no. 8, pp. 1244-1248, Aug. 1998.
[15] M. Waltari, and K. Halonen, “An 8-bit low-voltage pipelined ADC utilizing switched-opamp technique,” in Proc. 25th IEEE ESSCIRC, Sep. 1999, pp. 174- 177.
[16] P. T. F. Kwok, and H. C. Luong, “Power optimization for pipeline analog-to-digital converters,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 5, pp.549-553, May. 1999.
[17] A. M. Abo, and P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May. 1999.
[18] D. Nairn, “A 10-b 3 V 100 MS/s pipelined ADC,” in Proc. IEEE CICC., May 2000, pp. 257–260.
[19] I. Mehr, and L. Singer, “A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC,” IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 318-325, Mar. 2000.
[20] J. Goes, J. C. Vital, and J. Franca, Systematic design for optimization of pipelined ADCs. Boston, MA : Kluwer Academic, 2001
[21] W. Yang, D, Kelly, I. Mehr, M. T. Sayuk, and L. Singer, “A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist Input,” IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1931–1936, Dec. 2001.
[22] D. Y. Chang and U. K. Moon, “A 1.4-V 10-bit 25-MS/s pipelined ADC using opamp-reset switching technique,” IEEE J. Solid-State Circuits, vol. 38, no. 8, pp. 1401-1404, Aug. 2003.
[23] D. Miyazaki, S. Kawahito, and M. Furuta, “A 10-b 30-MS/s low-power pipelined CMOS A/D converter using a pseudodifferential architecture,” IEEE J. Solid-State Circuits, vol. 38, no. 2, pp. 369-373, Feb. 2003.
[24] B. Vaz, J. Goes, and N. Paulino, “A 1.5-V 10-b 50 MS/s time-interleaved switched-opamp pipeline CMOS ADC with high energy efficiency,” in Proc. VLSI Circuits Dig. Tech. Papers, June 2004, pp. 432-435.
[25] O. A. Adeniran, A. Demosthenous, C. Clifton, S. Atungsiri, and R. Soin, “A CMOS low-power ADC for DVB-T and DVB-H systems,” in Proc. IEEE ISCAS, May 2004, vol. 1, pp. 209-212.
[26] G. Bonfini, A. S. Brogna, C. Garbossa, L. Colombini, M. Bacci, S. Chicca, F. Bigongiari, N. C. Guerrini, and G. Ferri, “An ultralow-power switched opamp-based 10-B integrated ADC for implantable biomedical applications,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 1, pp. 174-178, Jan. 2004.
[27] X. Wang, P. J. Hurst and, S. H. Lewis, “A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration,” IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1799-1808, Nov. 2004.
[28] J. Li and U. K. Moon, “A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique,” IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1468-1476, Sep. 2004.
[29] S. Kawahito, K. Honda, M. Furuta, N. Kawai, and D. Miyazaki, “Low-power design of high-speed A/D converters,” IEICE Trans. Electron., vol. E88-C , no. 4, pp. 468-478, Apr. 2005.
[30] D. Y. Chang, G. C. Ahn, and U. K. Moon, “Sub-1-V design techniques for high-linearity multistage/pipelined analog-to-digital converters,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 1, pp. 1-12, Jan. 2005.
[31] T. N. Andersen, Bjørnar Hernes, A. Briskemyr, F. Telstø, J. Bjørnsen, T. E. Bonnerud, and Ø. Moldsvor, “A Cost-Efficient High-Speed 12-bit Pipeline ADC in 0.18-um Digital CMOS,” IEEE J. Solid-State Circuits, vol. 40, no. 7, pp. 1506-1513, Jul. 2005.
[32] O. A. Adeniran, A. Demosthenous, “A 19.5mW 1.5V 10-bit ADC for DVB-H systems in 0.35 um CMOS,” in Proc. IEEE ISCAS, May 2006, pp. 5351–5354.
[33] P. Y. Wu, V. S. L. Cheung, and H. Luong, “A 1-V 100MS/s 8-bit CMOS switched-opamp pipelined ADC using loading-free architecture,” IEEE J. Solid-State Circuits, vol. 42, No. 4, pp. 730-738, Apr. 2007.
[34] K. Honda, F. Mazanori, and S. Kawahito, “A 1V 30mW 10b 100MSample/s pipeline A/D converter using capacitance coupling technique,” in Proc. VLSI Circuits Dig. Tech. Papers, June 2006, pp. 224-225.
[35] H. C. Kim, D. K. Jeong, and W. Kim, “A partially switched-opamp technique for high-speed low-power analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 41, No. 8, pp. 1938-1943, Aug. 2006.
[36] O. A. Adeniran and A. Demosthenous, “An ultra-energy-efficient wide-bandwidth video pipeline ADC using optimized architectural partitioning,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 12, pp. 2485-2497, Dec. 2006.
[37] Y. J. Kim, H. C. Choi, S. W. Yoo, S. H. Lee, D. Y. Chung, K. H. Moon, H. J. Park, and J. W. Kim, “A Reconfigurable 0.5V to 1.2 V, 10 MS/s to 100 MS/s, low-power 10b 0.13 um CMOS pipeline ADC,” in Proc. IEEE CICC, Sep. 2007, pp. 185-188.
[38] P. N. Singh, A. Kumar, C. Debnath, and R. Malik, “20mW, 125 MSPS, 10-bit pipelined ADC in 65nm standard digital CMOS process,” in Proc. IEEE CICC, Sep. 2007, pp. 189-192.
[39] C.-C. Lu, and T.-S. Lee, “A 10-bit 60-MS/s low-power CMOS pipelined analog-to-digital converter,” IEEE Trans. Circuits Syst. II, Express briefs, vol. 54, no. 8, pp. 658-662, Aug. 2007.
[40] M. Yoshioka, M. Kudo, T. Mori, and S. Tsukamoto, “A 0.8V 10b 80 MS/s 6.5mW pipelined ADC with regulated overdrive voltage biasing,” in Proc. IEEE ISSCC. Dig. Tech. Papers, Feb. 2007, pp. 100-101.
[41] Y. D. Jeon, S. C. Lee, K. D. Kim, J. K. Kwon, and J. Kim, “A 4.7 mW 0.32 mm2 10b 30MS/s pipelined ADC without a front-end S/H in 90nm CMOS,” in Proc. IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp. 456-615.
[42] S. C. Lee, Y. D. Jeon, K. D. Kim, J. K. Kwon, J. Kim, J. W. Moon, and W. Lee, “A 10b 205 MS/s 1mm2 90nm CMOS pipeline ADC for flat-panel display applications,” in Proc. IEEE Dig. Tech. Papers, pp. 458-615, Feb. 2007.
[43] S. T. Ryu, B. S. Song, and K. Bacrania, “A 10-bit 50-MS/s pipelined ADC with opamp current reuse,” IEEE J. Solid-State Circuits, vol. 42, No. 3, pp. 475-485, Mar. 2007.
[44] J. Li, X. Zeng, L. Xie, J. Chen, J. Zhang, and Y. Guo, “A 1.8-V 22-mW 10-bit 30-MS/s pipelined CMOS ADC for low-power subsampling applications,” IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 321-329, Feb. 2008.
[45] M. Waltari and K. A. I. Halonen, “1-V 9-bit pipelined switched-opamp ADC,” IEEE J. Solid-State Circuits, vol. 36, no. 1, pp.129–134, Jan. 2001.
[46] H. H. Ou, S. J. Chang, and B. D. Liu “Low-power circuit techniques for low-voltage pipelined ADCs based on switched-opamp architecture,” IEICE Trans. Fundamentals, vol. E91-A, no. 2, pp.461-468, Feb. 2008.
[47] H. H. Ou, S. J. Chang, and B. D. Liu, “A power-efficient 0.8-V, 9-bit, 20-MS/s pipelined ADC with opamp-shared loading-free architecture”, in Proc. IEEE ICCCAS, May. 2008, pp. 1172-1175.
[48] B. R. Gregoire, and U. K. Moon, “An over-60dB true rail-to-rail performance using correlated level shifting and an opamp with 30dB loop gain,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp 540-541.
[49] H. H. Ou, B. D. Liu, “A 1-V, 9-Bit, 2.5-Msample/s pipelined ADC with merged switched-opamp and opamp-sharing techniques,” in Proc. IEEE ISCAS, May. 2005, pp. 1972-1975.
[50] R. Wang, D. J. K. Martin, and G. Burra, “A 3.3 mW 12MS/s 10bit pipelined ADC in 90 nm digital CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2005, pp.278–279.
[51] H. C. Kim, D.K. Jeong, and W. Kim, “A 30 mW 8 bit 200MS/s pipelined CMOS ADC using a switched-opamp technique,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2005, pp.284–285.
[52] A. Matsuzawa, “Mixed signal SoC era,” IEICE Trans. Electron., vol. E87-C, no.6, pp.867–877, June 2004.
[53] T. Adachi, A. Ishikawa, A. Barlow, and K. Takasuka, “A 1.4 V switched capacitor filter,” in Proc. IEEE CICC, May 1990, pp. 8.2.1-8.2.4.
[54] J. Crols, and M. Steyaert, “Switched-opamp: an approach to realize full CMOS switched-capacitor circuits at very low power supply voltages,” IEEE J. Solid-State Circuits, vol. 29, pp. 936-942, Aug 1994.
[55] A. Baschirotto, and R. Castello, “A 1-V 1.8-MHz CMOS switched-opamp SC filter with rail-to-rail output swing,” IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 1979-1986, Dec. 1997.
[56] V. S. L. Cheung, H. C. Luong and W. H. Ki, “A 1-V CMOS switched-opamp switched-capacitor pseudo-2-path filter,” IEEE J. Solid-State Circuits, vol. 36, no. 1, pp. 14-22, Jan. 2001.
[57] V. S. L. Cheung, H. C. Luong, and W. H. Ki, “A 1-V 10.7-MHz switched-opamp bandpass sigma-delta modulator using double-sampling finite-gain-compensation technique,” IEEE J. Solid-State Circuits, vol. 37, no. 10, pp. 1215-1225, Oct. 2002.
[58] D. W. Cline, “Noise, speed, and power trade-offs in pipelined analog to digital converters,” Ph.D. Dissertation, Univ. California, Berkeley, 1995.
[59] M. Dessouky and A. Kaiser, “Input switch configuration suitable for rail-to-rail operation of switched opamp circuits,” Electron.Lett., vol. 35, pp. 8-10, Jan. 1999.
[60] A. Baschirotto, R. Castello, and G. P. Montagna, “Active series switch for switched-opamp circuits,” Electron.Lett., vol. 34, pp. 1365-1366. Jul. 1998.
[61] R. –A. Ju, D. –H. Lee, and S. –D. Yu, “High-speed low-power CMOS pipelined analog-to-digital converter,” IEICE Trans. Fundamentals, vol. E82-A, no. 6, pp.981-986, June 1999.
[62] K. Nagaraj, H. S. Fetterman, J. Anidjar, S. H. Lewis, and R. G. Renninger, “A 250-mW, 8-b, 52-Msample/s parallel-pipelined A/D converter with reduced number of amplifiers,” IEEE J. Solid-State Circuits, vol. 32, no. 3, pp. 312-320, Mar. 1997.
[63] P. C. Yu and H. S. Lee, “A 2.5-V 12-b 5-MSample/s pipelined CMOS ADC,” in IEEE ISSCC Dig. Tech. Papers, Feb. 1996, pp. 314-315.
[64] B. M. Min, P. Kim, F. W. Bowman, D. M. Boisvert, and A. J. Aude, “A 69-mW 10-bit 80-MSample/s pipelined CMOS ADC,” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2031-2039, Dec. 2003.
[65] T. C. Choi and R. W. Brodersen, “Considerations for high-frequency switched-capacitor ladder filters,” IEEE Trans. Circuits Systs. CAS-27, pp. 545-552, 1980.
[66] H. H. Ou, B. D. Liu, and S. J. Chang, “A 0.8-V 250-MSample/s double-sampled inverse-flip-around sample-and-hold circuit based on switched-opamp architecture,” IEICE Trans. Electronics, to be published in Sep. 2008.
[67] M. Waltari and K. Halonen, “A 220-Msample/s CMOS sample-and-hold circuit using double-sampling,” Analog Integr. Circuits Process., vol. 18, no. 1, pp. 21–31, Jan. 1999.
[68] M. Waltari, K. Halonen, “Timing skew insensitive switching for double-sampled circuits,” in Proc. IEEE ISCAS, vol. II, pp. 61–64, May 1999.
[69] T. S. Lee, and C. C. Lu, “A 200 MHz 4.8 mW 3 V fully differential CMOS sample-and-hold circuit with low hold pedestal,” Analog Integr. Circuits Process., vol. 45, no. 1, pp. 37-46, Oct. 2005.
[70] A. Baschirotto, “A low-voltage sample-and-hold circuit in standard CMOS technology operating at 40 MS/s,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process, vol. 4, no. 4, pp. 394-399, Apr. 2001.
[71] T.-S. Lee and C.-C. Lu, “A 1.5-V 50-MHz pseudodifferential CMOS sample-and-hold circuit with low-hold pedestal,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 9, pp. 1752–1757, Sep. 2005.
[72] M. Keskin, “A novel low-voltage switched-capacitor input branch,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process, vol. 50, no. 6, pp. 315-317, June 2003.
[73] Y. Chiu, P. R. Gray, and B. Nikolić, “A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2139–2151, Dec. 2004.
[74] D. Y. Chang, “Design techniques for a pipelined ADC without using a front-end sample-and-hold amplifier,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 11, pp. 2123-2132, Nov. 2004.
[75] H. H. Ou, Y. C. Chen, and B. D. Liu, “A 0.7-V 10-bit 3μW analog-to-digital converter for implantable biomedical applications”, in Proc. IEEE BIOCAS, Nov. 2006, pp. 122-125.
[76] M. Waltari, “Circuit techniques for low-voltage and high-speed A/D converters,” Ph.D. Dissertation, Univ. Helsinki of Technology, Finland, 2002.
[77] P. J. Lim and B. A. Wooley, “A high-speed sample-and-hold technique using a miller hold capacitance,” IEEE J. Solid-State Circuits, vol. 26, no. 4, pp. 643-651, Apr. 1991.
[78] D. G. Haigh, B. Singh, “A switching scheme for switched capacitor filters which reduces the effect of parasitic capacitances associated with switch control terminals,” in Proc. IEEE ISCAS, 1983, pp. 586–589,
[79] N. Kurosawa, H. Kobayashi, K. Maruyama, H. Sugawara, and K. Kobayashi, “Explicit analysis of channel mismatch effects in time-interleaved ADC systems,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 48, no. 3, pp.261-271, Mar. 2001.
[80] B. Murmann and B. E. Boser, “A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification,” IEEE J. Solid-State Circuits, vol. 38, no. pp. 2040-2050, Dec. 2003.
[81] J. Li and U. Moon, “Background calibration techniques for multistage pipelined ADC’s with digital redundancy,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process, vol. 50, no. 9, pp. 531–538, Sept. 2003.
[82] O. Erdoğan, P. Hurst, and S. Lewis, “A 12-b digital-background-calibrated algorithmic ADC with -90-dB THD,” IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1812–1820, Dec. 1999.
[83] B. S. Song, M. F. Tompsett, and K. R. Lakshmikumar, “A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converter,” IEEE J. Solid-State Circuits, vol. 24, no. 6, pp. 1324-1333, Dec. 1988.

校內：2009-08-20公開
校外：2009-08-20公開

簡易檢索 / 詳目顯示

相關論文