本論文提出一些電路設計技巧來有效降低無線通訊系統中之電流導向式數位類比轉換器之功率消耗。此外，一個新型的複合式電流源單元也被提出，使系統單晶片中之電流導向式數位類比轉換器能擁有更多的功能以減少系統整合之成本和挑戰。因此，三個概念驗證之試製晶片被呈現出來驗證所提出之電路技巧。透過對所設計晶片之實際下線和量測驗證，證明所提出之電路技巧可以有效降低功率消耗，且這些晶片可以滿足並整合於無線通訊系統之應用，尤其非常適合超寬頻無線通訊系通之應用。本論文所提出之驗證晶片和電路技巧及晶片量測成果將簡述如下：
第一個驗證晶片為五位元1.35 GS/s 數位類比轉換器。此設計使用三位元溫度計編碼和兩位元二進位權重編碼之分段式架構來取得對電路複雜度和差分線性誤差之妥協。此外，此轉換器使用雙載子電流源單元來降低功率消耗並且維持系統所需之輸出振幅。此設計更提出一個突波抑制電路來減少時脈饋入效應所造成之雜訊。此轉換器使用標準0.18-um 1P6M互補式金屬氧化物半導體製程驗證，所佔據之晶片面積為0.19平方毫米。量測結果顯示此電路之積分非線性誤差和差分非線性誤差分別為0.04及0.05最低有效位元，且當電路操作在1.35 GS/s下，整個奈奎斯頻帶的無雜訊動態範圍皆大於30分貝，並且此電路總共只消耗9.7 毫瓦之功率。
第二個驗證晶片為六位元2.7 GS/s 數位類比轉換器。此設計使用二位元溫度計編碼和四位元二進位權重編碼之分段式架構來取得對電流源電晶體面積和溫度計碼解碼器速度之妥協。此設計並提出虛擬溫度計碼之解碼器架構來提升數位類比轉換器之動態效能。此外，此設計使用雙載子電流源單元和鎖存電路時脈延遲技巧來分別減少類比和數位部分之功率消耗。此設計並提出一個面積緊密的突波抑制電路來簡化傳統突波抑制電路之設計和面積。此數位類比轉換器使用標準0.13-um 1P8M互補式金屬氧化物半導體製程驗證，所佔據之晶片面積為0.0585平方毫米。量測結果顯示此電路之積分非線性誤差和差分非線性誤差分別為0.11及0.09最低有效位元，且當電路操作在2.7 GS/s下，整個奈奎斯頻帶之無雜訊動態範圍皆大於36分貝。此電路在輸出接近奈奎斯頻率時，總共消耗5.4 毫瓦之功率，且品質因素只有31 fJ/轉換步驟。
第三個驗證晶片主要提出一個具有N型，P型和雙載子電流源單元特性之複合式電流源單元，並且基於此單元實現一個具有高操作速度和輸出軌到軌振幅的數位類比轉換器。因此，此轉換器可以滿足通訊及軌到軌電壓源之應用。透過適當切換所提出之電流源和連接到外部的增益控制電阻，此轉換器在供應電壓為1.2伏特下，可以提供間距大約6.4 毫伏之電壓源訊號。此轉換器使用低功率90-nm 1P9M互補式金屬氧化物半導體製程驗證，所佔據的晶片面積為0.045平方毫米。當電路操作在3 GS/s下，整個奈奎斯頻帶之無雜訊動態範圍皆大於36分貝，在輸出接近奈奎斯頻率時，總共只消耗8.32 毫瓦之功率。

This dissertation proposes several circuit design techniques for current-steering digital-to-analog converters (DACs) on wireless communication applications to lower the power consumption. Moreover, a compound current cell is also proposed to make current-steering DACs in a system-on-a-chip (SoC) have more functionality for reducing the integration challenges and cost. Hence, three proof-of-concept prototypes are presented to demonstrate these techniques. According to the measurement results of the prototypes, the proposed techniques have good power efficiency and the prototypes can meet wireless communication applications, especially on ultra-wideband (UWB) applications. The prototypes and chip measurement results are depicted as follows:
The first one uses a “3 (thermometer)  2 (binary)” segmented structure for reaching a compromise between the circuit complexity and the differential nonlinearity (DNL) error. In addition, we employ bipolar current source cells in this prototype to cut the power consumption while maintaining the same output voltage swing. Moreover, a de-glitch latch is presented to reduce the clock feedthrough from the pass transistors. This prototype was implemented in a standard 0.18-m 1P6M CMOS technology with the active area of 0.19 mm2. The measured integral nonlinearity (INL) and DNL are less than 0.04 and 0.05 least significant bit (LSB), respectively. The measured spurious-free dynamic range (SFDR) is above 30 dB over the complete Nyquist band at the sampling frequency of 1.35 GHz. The power consumption of this DAC is 9.7 mW.
The second prototype is a 6-bit 2.7-GS/s DAC. In this prototype, a “2 (thermometer)  4 (binary)” segmented architecture is chosen to make a compromise between the current source cell’s area and the operating speed of the thermometer decoder. In addition, the proposed pseudo-thermometer structure improves the DAC’s dynamic performance. The bipolar current source cell and latch clock delay technique are employed to reduce the power consumption in analog and digital parts, respectively. Moreover, the compact de-glitch latch simplifies the conventional latch design and layout. This DAC was implemented in a standard 0.13-m 1P8M CMOS technology with the active area of 0.0585 mm2. The measured DNL and INL are less than 0.09 and 0.11 LSB, respectively. The measured SFDR is more than 36 dB over the Nyquist frequency at the sampling frequency of 2.7 GHz. The DAC consumes 5.4 mW for a near-Nyquist sinusoidal output at 2.7 GS/s, resulting in a better figure of merit of 31 fJ/conversion-step.
In the third one, a compound current cell, with the properties of N-type, P-type, and bipolar ones, is proposed and utilized in a current-steering DAC to satisfy the application of rail-to-rail voltage sources. Additionally, a DAC with the cells also has a high speed fashion. Therefore, the presented DAC with the cells meets both communication and rail-to-rail voltage-source applications. Moreover, the effective output voltage step size is improved by appropriately switching these cells and connecting one of gain control resisters, resulting in a about 6.4-mV step size in a 1.2-V supply. Furthermore, this DAC was implemented in a standard low-power 90-nm 1P9M CMOS technology with the active area of 0.045 mm2. The measured SFDR is more than 36 dB over the Nyquist frequency at 3 GS/s, and the DAC consumes 8.32 mW for a near-Nyquist sinusoidal output at the sampling rate of 3 GS/s.

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