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研究生： 陳健銘
Chen, Chien-Ming
論文名稱： 具主動箝位之高降壓順向轉換器
Forward Active Clamp High Step-Down Converter
指導教授： 陳建富
Chen, Jiann-Fuh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2023
畢業學年度： 111
語文別： 英文
論文頁數： 94
中文關鍵詞： 直流-直流電源轉換器 、箝位電路 、平板變壓器 、零電壓切換 、倍流電路 、數位控制
外文關鍵詞： DC-DC converter, active clamp circuit, planar transformer, zero-voltage switching, current-doubler circuit, digital control
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    • 本論文研製具主動箝位高頻高降壓隔離型直流直流電源轉換器，此轉換器主要應用於資料中心、微處理器、電腦供電系統。此轉換器使用平面變壓器與箝位電路來達到高切換頻率。此電路架構高壓側由箝位電容串聯變壓器使其達成高降壓，並且在箝位電容與變壓器並聯開關使其達成零電壓切換，並且使變壓器操作在一、三象限。低壓側則採用倍流電路整流，使其分流並且達成低輸出電流漣波，由於倍流電路具有電流相消特性，因此輸出電流漣波較小，更適合應用在低壓系統，例如CPU、GPU、伺服器系統。此轉換器可達到軟切換，減少開關的切換損失，因此更適合高頻以減少磁性元件的體積達到更高功率密度。本論文分析此電路之動作原理，並分析電壓增益曲線以及漣波電流之大小。本論文實作額定功率為54 W、切換頻率500kHz、直流輸入電壓48 V、輸出電壓1.8 V、輸出電流30 A之實驗雛形，實測最高效率可達91.8%，並使用數位訊號處理器TMS320F28379D電路之數位控制，暫態測試半載到滿載態時間約為200 μs。

    This thesis describes the development of an active clamp high-frequency, high step-down isolated DC-DC converter, which is mainly applied in data centers, microprocessors, and computer power systems. The proposed converter uses a planar transformer and two active clamp circuit to achieve high switching frequency. The high-voltage side of this circuit achieves high step-down ratio through a series connected clamp capacitor and transformer. Additionally, the parallel switches are connected to the clamp capacitor and transformer to achieve zero-voltage switching (ZVS) which allows the transformer to operate in the first and third quadrants. The low-voltage side adopts a current-doubler rectifier circuit to achieve low output current ripple. Since the current-doubler circuit has current-canceling characteristics, the output current ripple is reduced, making it more suitable for low-voltage systems such as CPUs, GPUs, and server systems. The converter can achieve soft switching, which reduces switching losses and more suitable for high frequency to reduce the volume of magnetic components and achieve higher power density.
    This thesis analyzes the operation principle of this circuit and then analyzes the voltage gain curve and the size of the ripple current. The rated power of the implemented prototype in this paper is 54 W, with a switching frequency of 500 kHz, a DC input voltage 48 V, an output voltage 1.8 V, and an output current of 30 A. The highest measured efficiency can reach 91.8%, and the circuit is controlled by a digital signal processor (DSP) TMS320F28379D. The transient response time is around 200 μs when load transition from half load to full load.

    摘要 I Abstract II 誌 謝 III CONTENTS IV List of Tables VII List of Figures VIII CHAPTER 1 INTRODUCTION 1 1.1. Background and Motivation 1 1.2. Thesis Outline 3 Chapter 2 REVIEW TOPOLOGIES OF HIGH STEP-DOWN CONVERTER 4 2.1 Non-isolated Buck Converter 4 2.1.1 Typical Buck Converter 5 2.1.2 Multi-phase Buck Converter 6 2.1.3 Tapped Inductor Buck Converter 7 2.1.4 ZVS Tapped Inductors Buck Converter 8 2.1.5 Dual Inductors Hybrid Converter 9 2.1.6 Summary of Non-isolated Topology 10 2.2 Isolated Converters with PWM (Pulse Width Modulation) Control 10 2.2.1 Forward Converter 12 2.2.2 Active Clamp Forward Converter (ACF) 13 2.2.3 Active Clamp Forward Converter with CDR 14 2.2.4 Three-Switch Active Clamp Forward Converter 15 2.2.5 Isolated Stacked Half-Bridge Converter with CDR (ISHBC) 16 2.2.6 Multiphase VRM Based on Symmetrical Half-Bridge 18 2.2.7 Summary of Isolated Topology 20 Chapter 3 OPERATION MODE ANALYSIS OF PROPOSED CONVERTER 22 3.1 Introduction of Proposed Converter 22 3.2 Operating principles of Proposed Converter 24 3.2.1 Mode Analysis of Proposed Converter 25 3.2.2 Steady State Analysis of Proposed Converter 41 CHAPTER 4 PARAMETER DESIGN AND DIGITAL COMPENSATOR 50 4.1 Parameter Design of the Proposed DC-DC Converter 50 4.2 Planar Transformer 53 4.3 Digital Compensator Design 58 CHAPTER 5 SIMULATION AND EXPERIMENTAL RESULTS 62 5.1 Simulation Results 63 5.1.1 ZVS Conditions of Switches 63 5.1.2 Waveforms of CDR Current 64 5.1.3 Bode Plot of Digital Compensator 68 5.2 Experimental Results 70 5.2.1 ZVS Condition 71 5.2.2 Output Ripple Voltage 74 5.2.3 Current Cancellation of CDR 80 5.2.4 Transient Response of Digital Controller 85 5.3 Efficiency Analysis 87 5.3.1 Efficiency 87 5.3.2 Efficiency Analysis 87 CHAPTER 6 CONCLUSIONS AND FUTURE WORKS 91 6.1 Conclusions 91 6.2 Future Works 91 REFERENCE 92

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