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研究生: 謝呈榆
Hsieh, Cheng-Yu
論文名稱: 以氧化亞錫作為閘極氧化層之III族氮化物高電子遷移率電晶體
The SnOx gate oxide-based III-Nitride High Electron Mobility Transistors
指導教授: 莊文魁
Chuang, Ricky Wen-Kuei
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics
論文出版年: 2017
畢業學年度: 105
語文別: 中文
論文頁數: 98
中文關鍵詞: 氧化亞錫氮化鎵濺鍍高電子遷移率電晶體
外文關鍵詞: Tin-monoxide, GaN, sputter, HEMT
相關次數: 點閱:67下載:6
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  • 本論文利用p型材料氧化亞錫作為閘極氧化層來探討氮化鋁鎵/氮化鎵高電子遷移率電晶體臨界電壓之調變。藉由控制氧通量來濺鍍氧化亞錫與後退火處理以達成高電洞濃度之薄膜。氧化亞錫薄膜在此研究扮演抬升傳導帶高於費米能階的功用,高電洞濃度的薄膜可使空乏型的高電子遷移率電晶體的臨界電壓往正值調變。
    氧化亞錫,是一種低成本、地球產量豐富以及無毒性的材料,被發表為一種p型的半導體。在本論文之中,我們將對製備完成後的氧化亞錫薄膜進行晶相分析、X光光電子能譜儀分析、表面粗糙度分析、霍爾濃度分析等,進一步探討薄膜特性,最後發現在4%與8%的通氧量下與150度到250度的藉由霍爾量測儀所能量到測的電洞濃度介於1019~1021cm-3,接著再利用晶相分析、X光光電子能譜儀分析,確保氧化亞錫薄膜能表現出p型半導體的特性。
    接著以氧化亞錫作為氮化鋁鎵/氮化鎵高電子遷移率電晶體之閘極氧化層,來探討高電子遷移率電晶體之元件特性。在8%氧通量的環境下與150度低溫退火成功的讓氮化鋁鎵/氮化鎵高電子遷移率電晶體的臨界電壓,由-4.2V往-3.6V移動,讓臨界電壓移動了0.6V。

    In this study, GaN based High Electron Mobility Transistors (HEMT) with p-type SnOx as gate oxide layer was presented. The SnOx thin film was prepared by RF sputtering coupled with post annealing. The SnOx was believably functioned as a p-type semiconductor. However, its reliability remains to be a major concern since the inherently narrow window of p-type SnOx sensitively depends on the pressure and oxygen flow rate chosen during the sputtering process and post annealing temperature. It is known that Sn occurs in two possible oxidation states, Sn2+ and Sn4+, among which tin oxide (Sn4+) appears to be a thermodynamically stable phase. Here, the several p-type SnOx films were investigated by varying the oxygen partial pressure (OPP=PO2/(PAr+PO2)) from 4 to 16%, followed by a post annealing performed at temperatures as low as 150 to 250oC in pure N2 environment to achieve high hole concentration. The SnOx has a sizable hole concentration in the range of 10^19-10^21 cm-3 as the oxygen partial pressure and temperature varied from 4 to 8% and 150 to 250oC, respectively. We also employ SnOx as a gate oxide layer for D-mode GaN based HEMT as an avenue to investigate the Vth shift. It is highly anticipated that incorporating the SnOx as a capping layer helps to achieve a normally off GaN HEMT. GaN HEMT with p-type tin-monoxide as capping layer was evaluated with the threshold voltage shifting from -4.2 to -3.6 V, corresponding to the SnOx film prepared at oxygen partial pressure of 8% and 150oC post annealing.

    目錄 中文摘要 I 英文摘要 III 誌謝 VIII 目錄 IX 表目錄 XI 圖目錄 XII 第一章 緒論 1 1-1 氮化鋁鎵/氮化鎵高電子遷移率電晶體演進與發展 1 1-2 氮化鎵材料特性及其應用 2 1-2.1 二維電子氣 4 1-3 論文架構 5 參考文獻 7 第二章 文獻回顧 10 2-1氮化鋁鎵/氮化鎵高電子遷移率電晶體 10 2-2 增強式氮化鋁鎵/氮化鎵高電子遷移率電晶體的做法 11 2-2.1閘極掘入 12 2-2.2氟離子佈植 13 2-2.3 p型材料 13 2-2.4電子儲存層 15 2-2.5隧道接面結構 16 2-3研究動機 16 2-4氧化亞錫 17 2-4.1氧化亞錫之結構與基本特性 18 2-4.2氧化亞錫的能階與缺陷 19 參考文獻 22 第三章 氧化亞錫薄膜研製與分析 25 3-1氧化亞錫薄膜研製 25 3-2 氧化亞錫材料分析 26 3-2.1 X-射線繞射分析(X-Ray Diffraction,XRD) 26 3-2.2 X光光電子能譜儀(XPS) 30 3-2.3原子力顯微鏡及掃描電子顯微鏡(AFM&SEM) 41 3-2.4霍爾效應分析 49 3-3本章結論 50 參考文獻 51 第四章 元件製作 53 4-1平台隔離(mesa isolation) 54 4-2歐姆接觸(Ohmic contact) 57 4-2.1表面處理 57 4-2.2歐姆接觸之金屬蒸鍍 57 4-2.3舉離製程(lift-off process) 58 4-3閘極製作(gate contact) 61 4-3.1蕭特基接觸之金屬蒸鍍 61 4-4製程完成圖 65 參考文獻 67 第五章 元件量測分析 68 5-1試片結構 68 5-2輸出特性曲線 70 5-3轉移特性曲線 77 5-4汲極漏電流 84 5-5閘極漏電流 89 5-6本章結論 93 參考文獻 94 第六章 結論與未來展望 95 6-1結論 95 6-2未來展望 97 參考文獻 98

    第一章
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    第二章
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    第三章
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    第四章
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    第五章
    [1] J. Lee, D. Liu, H. Kim, and W. Lu, "Post-annealing effects on device performance of AlGaN/GaN HFETs," Solid-State Electronics, vol. 48, pp. 1855-1859, 2004/10/01/ 2004.

    第六章
    [1] S. Dayal, S. Kumar, S. Kumar, H. Arora, R. Laishram, R. K. Chaubey, et al., "Passivation of AlGaN/GaN HEMT by Silicon Nitride," in Physics of Semiconductor Devices: 17th International Workshop on the Physics of Semiconductor Devices 2013, V. K. Jain and A. Verma, Eds., ed Cham: Springer International Publishing, 2014, pp. 141-143.
    [2] F. Lee, L. Y. Su, C. H. Wang, Y. R. Wu, and J. Huang, "Impact of Gate Metal on the Performance of p-GaN/AlGaN/GaN High Electron Mobility Transistors," IEEE Electron Device Letters, vol. 36, pp. 232-234, 2015.

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