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研究生： 陳建弘
Chen, Chien-Hung
論文名稱： 採用運算放大器共享技術之低電壓管線式類比數位轉換器
Low-Voltage Pipelined A/D Converter Using Opamp-Sharing Technique
指導教授： 劉濱達
Liu, Bin-Da
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2006
畢業學年度： 94
語文別： 中文
論文頁數： 66
中文關鍵詞： 管線式類比數位轉換器
外文關鍵詞： pipelined A/D converter
相關次數： 點閱：101  下載：8 
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    • 本論文中，使用TSMC 0.13 微米一層多晶矽八層金屬之互補式金氧半製程，提出一個具有十位元解析度且每秒取樣十百萬次的管線化類比數位轉換器。為了能夠使這個管線化類比數位轉換器能夠操作在供應電壓只有0.7伏特的情況下，在運算放大器的設計上中融合了具有可靠性解決方案的切換式運算放大器技術和運算放大器共享技術。藉著這些方法，設計出一個具有雙輸出端的運算放大器。這個管線化類比數位轉換器的第一級包含了前端取樣和保留電路(sample-and-hold, S/H)和具有放大倍率的類比數位轉換器使用切換式運算放大器(multiplying–digital-to-analog converter, MDAC)兩種電路。整個十位元的類比數位轉換器只用了五級的運算放大器。如此不但達到在低電壓下操作的要求，更減少了整個類比數位轉換器的功率消耗。
    在電路模擬方面，經由HSPICE輔助設計軟體驗證結果。這個具十位元解析度每秒取樣十百萬次的管線化類比數位轉換器，在取樣頻率十百萬赫茲輸入訊號兩百千赫茲下訊號對於雜訊及諧波失真比為 58.44 dB，在供應電壓0.7伏特下，整個電路的功率消耗為 19 mW。

    In this thesis, a 10-bit 10-MHz pipelined analog-to-digital converter (ADC) consisted of 1.5-bit/stage has been designed and implemented in the TSMC 0.13-µm 1P8M CMOS process. In order to operate at 0.7 V, the pipelined analog-to-digital converter merges both switched-opamp and opamp-sharing techniques. An opamp with two output stages is employed to incorporate opamp-sharing technique into conventional switched-opamp circuit structure. Low voltage sample-and-hold (S/H) and multiplying–digital-to-analog converter (MDAC) stages utilizing the developed dual-output opamp are introduced. In this work, the ADC is realized in five stages. So, the proposed pipelined ADC can operate under low power supply and reduces the total power consumption.
    The A/D converter is simulated by HSPICE. The signal-to-noise and distortion ratio (SNDR) of the pipelined ADC is 58.44 dB with sampling frequency of 10 MHz at input frequency 200 kHz. Power consumption of this ADC is 19 mW with 0.7 V power supply.

    TABLE OF CONTENTS II ABSTRACT IV LIST OF FIGURES VI LISTS OF TABLES IX CHAPTER 1 INTRODUCTION 1 1.1 Motivation 1 1.2 Thesis Organization 3 CHAPTER 2 PIPELINED A/D CONVERTER AND SC CIRCUIT 4 2.1 Pipelined A/D Converter Architecture 5 2.2 Low-Voltage Switch-Capacitor Technique 7 2.2.1 Floating Switch Problem at Low Supply Voltage 8 2.2.2 Clock Voltage Multiplier 11 2.2.3 Principle of Switched-Opamp Technique 12 2.3 Amplifier Sharing Technique 13 2.4 Summary 15 CHAPTER 3 DESIGN OF A 10-BIT PIPELINED A/D CONVERTER 16 3.1 Specification of Pipelined A/D converter 17 3.1.1 Conventional Switched-Capacitor Configuration 18 3.2.2 Switched-Opamp Configuration 21 3.2 Low-Voltage Sample-and-Hold Circuit 25 3.2.1 Implementation of Sample-and-Hold Circuit 26 3.2.2 Bootstrapped Switch 27 3.2.3 Simulation Results of S/H 30 3.3 Design of Multiplying Digital-to-Analog Converter 32 3.3.1 Conventional MDAC of 1.5-Bit/Stage Pipelined Architecture 32 3.3.2 Low-Voltage MDAC Circuit 35 3.4 Summary 39 CHAPTER 4 CIRCUIT DESIGN AND SIMULATION RESULTS 40 4.1 Switchable-Opamp Circuit 41 4.1.1 Design of Switchable-Opamp 43 4.1.2 Common-Mode Feedback Circuit 45 4.1.3 Simulation Results of Opamp 47 4.2 Low-Voltage Comparator and Sub-ADC 49 4.2.1 Low-Voltage Comparator 49 4.2.2 Sub-ADC 53 4.2.3 Clock Generator 54 4.3 Simulation Results of Low-Voltage Pipelined A/D Converter 56 4.4 Summary 60 CHAPTER 5 CONCLUSIONS 61 5.1 Conclusions 61 5.2 Future Work 62 REFERENCES 63

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