雙環式計數器(Twisted-Ring Counters,TRCs)被運用在內建式自我測試向量產生器(Test Pattern Generator)，僅需較小的電路面積與簡單的控制就可對高效電路進行測試向量產生，且不會在待測電路的關鍵路徑(Critical path)上增加額外的邏輯閘，因此對效能的影響可以被忽略。但由於單雙環式計數器(Single TRC)常需要較長的測試時間和大量的測試資料量以達到100%的故障覆蓋率(Fault Coverage)。在這篇論文，一個新的基於多重雙環式計數器(Multiple TRC)的測試向量產生方法被提出來用以降低所需要的測試時間和所需要的測試資料量。其概念上是指將待測電路上的掃描路徑(Scan Path)分割成多個相同長度的多重掃描區段(multiple scan segments)，每個區段(segments)都加上的TRC設計去做自我測試向量產生。為了降低所需要的測試資料量，我們也發展出有效的演算法對不同的待測電路(Circuit Under Test)去決定出所需要的測試資料以及控制訊號。實驗結果顯示，使用我們的方法只需要增加少量的控制電路就可以大幅減少所需要的測試資料量。以ISCAS’89、ITC’99和IWLS’05的標準電路為例，使用我們提出的方法與過去的方法比較，在單雙環式計數器(Single TRC)的情形下，我們的方法僅需儲存少量的測試資料就可以大幅減少所需要的測試時間，其減少幅度在49.72 - 98.22%間。另外，同樣使用我們方法在多重雙環式計數器(Multiple TRC)的情形之下，只需比單雙環式計數器情形下增加少量的測試資料就可以更進一步大幅降低高達86.49 - 99.44%的測試時間。在大型電路中，我們的方法僅需0.11% - 1.55%的電路面積(Area Overhead)。

Twisted-ring-counters (TRCs) have been used as built-in test pattern generators for high-performance circuits due to their small area overhead, low performance impact and simple control. However previous work based on a single TRC often requires long test time and may require large storage data volume for complete testing. In this thesis a novel multiple-TRC based on-chip test generation scheme is proposed to minimize both the required test application time and the total number of required seeds. The scan path of a circuit under test is divided into multiple equal-length scan segments, each equipped with a small-size TRC design together with a reconfigurable control logic unit for concurrent test generation. An efficient algorithm to determine the required seeds and the control vectors is developed. Experimental results on ISCAS’89, ITC’99 and IWLS’05 benchmark circuits show that on average the proposed scheme using only one TRC design can achieve 49.72-98.22% reductions on the number of test application cycles with much smaller storage data volume compared with previous work. When using more TRC designs, 86.49-99.44% reductions can be achieved with only slight increase on test data volume. Also the proposed scheme requires only 0.11-1.55% area overhead for large circuits.

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