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研究生： 林韋德
Lin, Wei-Te
論文名稱： 應用於電流汲取式數位類比轉換器之動態性能提升技術
Dynamic-Performance-Improved Techniques for Nyquist-Rate Current-Steering DACs
指導教授： 郭泰豪
Kuo, Tai-Haur
學位類別： 博士
Doctor
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2013
畢業學年度： 101
語文別： 英文
論文頁數： 116
中文關鍵詞： 數位類比轉換器 、電流汲取式 、二元權重 、高速 、高解析 、尼奎式 、無失真動態範圍 、三階互調失真 、精簡面積 、動態元件匹配 、歸零 、數位歸零 、性能評比 、隨機旋轉二元選擇 、動態元件匹配結合數位歸零 、誤差免疫
外文關鍵詞： DAC, current-steering, binary-weighted, high-speed, high-resolution, Nyquist rate, SFDR, IM3, compact size, DEM, RTZ, DRZ, FoM, RRBS, DEMDRZ, mismatch insensitivity
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    • 電流汲取式數位類比轉換器(DAC)廣泛使用於高速應用。在此論文中，多項適用於Nyquist-rate電流汲取式DAC的動態性能提升技術被提出。
    針對低成本DAC設計，我們提出一個名為”隨機旋轉二元選擇(RRBS)”以實現動態元件匹配(DEM)技術。RRBS具有像二元權重編碼架構(binary-weight)一樣的精簡電路，卻能大量的降低電流源不匹配效應。相較於傳統二元權重編碼架構，RRBS具較佳的電流源切換特性，隨機選擇本質上即降低了Nyquist輸出頻率的突波發生。雖然RRBS的電流源切換量較溫度計編碼增加些許，但其不採用溫度計編碼電路將節省更多的晶片面積。我們以0.18微米1.8V CMOS製程實現一個10位元採用RRBS技術的DAC，主動面積僅為0.034平方毫米。量測結果顯示，在500MS/s取樣下，整個Nyquist頻寬(<250MHz)皆可達到 >61dB 無失真動態範圍(SFDR)，而其主動面積小於世界一流文獻中所載錄的10%。其SFDR性能甚至可比擬12位元DAC。以三個常見的性能指標(FoM)評比我們所提出的RRBS DAC及發表於世界一流文獻之10~12位元DAC。我們在其中兩項FoM中得到最佳評比。
    針對高解析DAC設計，我們提出了新穎的佈局方式，名為”一線到底(OLR)”，結合DEM技術十分適合用來降低電路成本。我們所提出的OLR方法，相較於多數己發表技術而言具有低複雜度、較短繞線距離、較小寄生電容等特色，並具有極佳的梯度誤差補償能力。我們以0.18微米1.8V CMOS製程實現一個14位元採用OLR+RRBS方法的DAC。量測結果顯示，在300MS/s取樣下，低頻輸出下可得到>80dB SFDR，Nyquist頻率輸出下可得到>70dB SFDR。晶片的主動面積僅0.18平方毫米，小於多數一流文獻所提出的DAC。
    針對高速DAC設計，我們提出一個結合DEM與數位歸零技術(DRZ)的創新架構(DEMDRZ)，以同時解決電流源誤差及切換突波造成的非線性。因此，本設計採用小面積電流源與電流開關並不會受到電流誤差影響，相反地，更能提升高頻輸出訊號的SFDR性能。我們採用DEMDRZ技術，我們以40奈米 CMOS製程實現一個12位元操作於1.6 GS/s的DAC。量測結果顯示，在1.6 GS/s取樣下，整個Nyquist頻寬(<800MHz)皆可達到>70dB SFDR，而在2.8GS/s取樣下，皆可達到< -61dB的三階交互調變失真(IM3)。可分別滿足訊號產生儀器(signal generation instrumentation)及多載波頻率通訊系統(multi-carrier communication system)不斷提升的應用需求。再者，在單電源1.2V下僅消耗40毫瓦。晶片主動面積僅0.016平方毫米，小於一流文獻DAC所需面積的5%。據我們所知，我們以DEMDRZ所實現的DAC實現出全球最佳的性能指標。

    Current-Steering Digital-to-Analog Converters (DACs) are widely used in high–speed applications. In this dissertation, several dynamic-performance-improved techniques for Nyquist-rate current-steering DACs are presented.
    For low-cost DAC designs, a DEM method, random rotation-based binary-weighted selection (RRBS), is proposed which offers the circuit simplicity that using binary- weighted coding and greatly reduces the mismatch effect. Compared with the conventional binary-weighted architecture, the switching activity of RRBS is improved and the glitch energy issues are inherently reduced by randomization. Although its switching activity is not near-minimum, the binary-to-thermometer decoder is not required, thereby further saving chip area. A 10-bit RRBS DAC is implemented with only 0.034 mm2 in a 0.18μm CMOS process. Measured performance achieves >61 dB spurious-free dynamic range (SFDR) in the Nyquist bandwidth with 500 MS/s, while its active area is less than one-tenth of that required by state-of-the-art 10-bit current steering DACs. Its SFDR is also comparable to that of 12-bit published designs. Three popular figures-of-merit (FoMs) are used to compare this design with other state-of-the-art 10~12-bit DACs, with the proposed design performing best with 2 FoMs.
    For high-resolution DACs, A novel layout pattern, i.e., one-line-routing (OLR), incorporating with DEM method for low-cost current-steering DACs is proposed. The proposed OLR method exhibits good gradient error compensation with low complexity and small metal routing overhead compared with most published methods, and induces less parasitic capacitance. With the proposed OLR incorporating with DEM, a 14-bit current-steering DAC is implemented in a 0.18μm CMOS process. The measured SFDR exceeds 80 dB at low output frequency and maintains 70 dB at near Nyquist output frequency clocked at 300 MS/s. The DAC has an active area of less than 0.18 mm2, which achieves a smaller active area than most of the state-of-the-art 14-bit DACs.
    For high-speed, high-resolution DACs, a technique utilizing dynamic-element- matching and digital return-to-zero, called DEMDRZ, is proposed to simultaneously suppress the mismatch- and transient-induced nonlinearity. In doing so, the usage of small-sized current sources and switches is possible, and the spurious-free dynamic range (SFDR) and third-order intermodulation distortion (IM3) for high signal frequencies can be improved. A 12-bit compact, low-power, high-speed, DAC is implemented in TSMC 40nm CMOS process. The implemented DAC achieves >70 dB SFDR for signals over the 800 MHz Nyquist bandwidth at 1.6 GS/s and < -61 dB IM3 for signals over the 1.4 GHz Nyquist bandwidth at 2.8 GS/s. Further, it dissipates 40 mW with a single 1.2 V supply. The active area of the DAC is 0.016 mm2, which is less than 6% of other state-of-the-art 12-bit current steering DACs. Furthermore, the implemented DAC performs best with three common figure-of-merits (FoMs).

    Abstract (Chinese) …………………………………………………………………… I Abstract (English) ……………………………………………………………………III Acknowledgements ………………………………………………………………… V Contents ………………………………………………………………………………VI List of Tables ………………………………………………………………………… IX List of Figures………………………………………………………………………… X 1 Introduction ………………………………………………………………………… 1 1.1 Motivation ………………………………………………………………………… 1 1.2 Design Considerations ………………………………………………………… 5 1.2.1 Decoding Architecture of a DAC …………………………………………… 5 1.2.2 Current Source Matching Issues …………………………………………… 7 1.2.3 Output Impedance Requirements ………………………………………… 13 1.2.4 Nonlinearity Due to Switching Transient ………………………………… 16 1.3 Organization …………………………………………………………………… 19 2 Random Rotation-Based Binary-Weighted Selection (RRBS) Method …… 21 2.1 Introduction …………………………………………………………………… 21 2.2 RRBS Principle and Mismatch-Insensitive Property ……………………… 23 2.2.1 Operating Principle of RRBS and traditional DACs ……………………… 23 2.2.2 Behavioral Verification of the DACs ……………………………………… 26 2.3 Dynamic Performance of RRBS DACs ……………………………………… 28 2.3.1 Switching Activity of the RRBS DAC ……………………………………… 28 2.3.2 Timing Skew Randomization ……………………………………………… 31 2.4 A 10-Bit DAC Implementation Using RRBS ………………………………… 32 2.4.1 Architecture Design and Area Cost Optimization ………………………… 32 2.4.2 Circuit Design and Implementation ………………………………………… 38 2.4.3 Measurement Results and Performance Comparison …………………… 41 2.5 Summary ………………………………………………………………………… 50 3 One-Line-Routing (OLR) of Current-Source Allocation for High-Resolution Current-Steering DACs …………………………………………………………… 51 3.1 Introduction ……………………………………………………………………… 51 3.2 Layout Techniques for Gradient Mismatch Compensation ……………… 52 3.2.1 Prior Published Layout Patterns, Q random Rotated Walk ……………… 53 3.2.2 Proposed One-Line-Routing Method ……………………………………… 56 3.3 A 14-Bit DAC Implementation Using the OLR Pattern …………………… 59 3.3.1 Matching Requirements and Circuit Design of Current Cell …………… 59 3.3.2 Chip Implementation ………………………………………………………… 62 3.4 Measurement Results and Comparisons …………………………………… 65 3.5 Summary ………………………………………………………………………… 71 4 Dynamic-Element-Matching and Digital Return-to-Zero Combination (DEMDRZ) Technique for High-Speed Current-Steering DACs ……………… 72 4.1 Introduction ……………………………………………………………………… 72 4.2 DEM and DRZ Combination (DEMDRZ) …………………………………… 74 4.2.1 Digital Return-to-Zero (DRZ) ……………………………………………… 75 4.2.2 Operation Principle ………………………………………………………… 76 4.2.3 Code Dependency …………………………………………………………… 78 4.3 A 12-Bit DAC Implementation Using DEMDRZ …………………………… 79 4.3.1 Circuit Design ………………………………………………………………… 81 4.3.2 Mismatch Verification ……………………………………………………… 86 4.3.3 Layout Floorplan …………………………………………………………… 92 4.4 Experimental Results ………………………………………………………… 94 4.4.1 Measurement Setup ………………………………………………………… 94 4.4.2 Measurement Results ……………………………………………………… 95 4.4.3 Performance Comparisons ………………………………………………… 99 4.5 DEM-assisted DRZ (DDRZ) ………………………………………………… 104 4.5.1 Circuit Block Diagram ……………………………………………………… 104 4.5.2 Measurement Results ……………………………………………………… 105 4.5.3 Verification of the DDRZ …………………………………………………… 107 4.6 Summary ……………………………………………………………………… 107 5 Conclusions ……………………………………………………………………… 108 Reference ………………………………………………………………………… 110 Curriculum Vitae ………………………………………………………………… 115

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