| 研究生: |
杜元偉 Du, Yuan-Wei |
|---|---|
| 論文名稱: |
適用於液晶顯示器之新式非晶矽/非晶相銦鎵鋅氧化物閘極驅動電路設計 Design of New a-Si:H/a-IGZO Gate Driver Circuits for TFT-LCD Applications |
| 指導教授: |
林志隆
Lin, Chih-Lung |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2014 |
| 畢業學年度: | 102 |
| 語文別: | 中文 |
| 論文頁數: | 56 |
| 中文關鍵詞: | 非晶矽薄膜電晶體 、非晶相銦鎵鋅氧化物電晶體 、閘極驅動電路 、功率消耗 |
| 外文關鍵詞: | Amorphous silicon thin-film transistor, amorphous In-Ga-Zn-O thin-film transistor, gate driver circuit, power consumption |
| 相關次數: | 點閱:133 下載:0 |
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近年來,為降低面板的成本,主動式液晶顯示器之閘極驅動電路採用薄膜電晶體技術設計已逐漸成為主流的趨勢。然而非晶矽薄膜電晶體元件會因為長時間的操作或是高偏壓的施加而產生臨界電壓的漂移,進而影響到驅動電路的穩定度,使得面板顯示的畫面失真。此外,為了符合窄邊框面板的需求以提高同尺寸面板的顯示面積,因此簡化非晶矽閘極驅動電路的架構並縮小其佈局面積亦為一重要之議題。另一方面,非晶相銦鎵鋅氧化物電晶體大多為空乏型元件,其臨界電壓為負值,因此解決其漏電流問題導致驅動電路的不正確操作以及降低功率消耗為a-IGZO閘極驅動電路的設計重點。
針對上述之問題,本論文提出三個新式非晶矽閘極驅動電路與二個新式非晶相銦鎵鋅氧化物閘極驅動電路,並經由電路模擬軟體證明所提出電路之可行性。第一個非晶矽閘極驅動電路由四顆電晶體與二顆電容所組成,藉由其精簡的電路架構縮減電路之佈局面積,使其能應用在窄邊框面板中,且利用交流式驅動方法來減緩電路中電晶體臨界電壓漂移的現象。模擬結果顯示,此電路能成功地將輸出節點充電至高電位,其輸出點充、放電達穩態所需時間分別為6.1 μs和5.1 μs。第二個非晶矽閘極驅動電路由四顆電晶體與三顆電容所組成,此電路針對第一個電路做改進,藉由增強輸入電晶體的驅動力以減少其所需之尺寸,使電路能更適用於窄邊框面板,且透過反向之電容耦合的方式,抑制雜訊的產生。根據模擬結果,此電路能夠有效地改善雜訊並輸出穩定的電壓波形,其輸出點充、放電達穩態所需時間分別為7.4 μs和5.5 μs。第三個非晶矽閘極驅動電路僅由二顆電晶體與三顆電容所構成,進一步降低電路佈局面積使電路能符合窄邊框面板的需求,且結合交流式驅動與反向之電容耦合的方法,抑制電路中電晶體臨界電壓漂移的現象與雜訊的產生。模擬結果證明,此電路能抑制雜訊並成功地輸出波形,其輸出點充、放電達穩態所需時間分別為9.4 μs和5.7 μs。第四個電路為非晶相銦鎵鋅氧化物閘極驅動電路,由八顆電晶體與兩顆電容所組成,藉由使用兩組時脈訊號與兩組低電壓準位電源,將電路中的電晶體完全關閉,進而抑制漏電流以達到低功率消耗的特點。模擬結果顯示,本電路能成功操作在空乏型或是增強型電晶體當中,輸出點充、放電達穩態所需時間分別為6.7 μs和5.3 μs,功率消耗與先前文獻所提出的閘極驅動電路相比可改善18.9 %。第五個電路由十一顆非晶相銦鎵鋅氧化物電晶體與兩顆電容所構成,透過將直流電壓源(VDD)作為驅動訊號且連接至驅動TFT之汲極端以降低時脈訊號的電容負載,進而減少時脈訊號之動態功率消耗。並藉由使用一組時脈訊號與兩組低電壓準位電源,使電路中全部TFT在關閉時皆操作在截止區,進而抑制漏電流的產生,達到低功率消耗的特點。根據模擬結果,本電路能成功操作在空乏型或是增強型電晶體當中,功率消耗與先前文獻所提出的閘極驅動電路相比可減少8.3 %。
This thesis presents five new gate driver circuits, including three amorphous silicon thin-film transistor (a-Si:H TFT) circuits and two amorphous In-Ga-Zn-O (a-IGZO) TFT circuits. For applying to the slim border panel, three new a-Si:H gate driver circuits are all simple structure to reduce the layout area. Moreover, three a-Si:H gate driver circuits utilize the AC-driving method to suppress the VTH shift of a-Si:H TFT. On the other hand, in order to prevent the incorrect circuit operation and reduce the power consumption which caused by the leakage current of a-IGZO TFTs, all TFTs can be completely turned off in the two proposed a-IGZO gate drivers. The feasibility of the proposed gate driver circuits are verified through the Hspice simulator. Based on the simulation results, three a-Si:H gate drivers can successfully generate output waveforms with simple circuit structure, and two a-IGZO gate drivers can achieve low-power consumption by suppressing the leakage current.
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校內:2019-08-21公開