在本論文中，我們主要探討應用於音頻使用的類比四階超取樣調變器電路設計的完整流程，超取樣調變器在音頻上使用已是很普遍的應用，但四階feedforward(FF)架構在國內尚未被廣泛的討論，因為在高階架構電路不穩定的問題上係數的推導是個難解的問題，並且在SPICE的模擬上是個非常耗時的程序，因此在本論文中我們介紹了完整的設計流程及在設計時有效利用行為模式大量的減少設計時間，並減少過度設計的時間和效能的浪費，電路的設計上提出了一個對稱性疊接運算放大器及高速低功率比較器，包含設計方法及實際效能，對於有興趣從事類比高階超取樣調變器設計者，相信是個很好的參考文獻，最後設計規格為四階、320倍超取樣、單一位元超取樣調變器電路，採用TSMC 2.5V, 0.25μm, 1P5M mixed-mode CMOS process 製作電路，在輸入訊號20k Hz時最大訊號對雜訊和失真比(PSNR)為87.1dB，取樣頻率12.8M Hz下總功率消耗為17.7mW。

　　In this thesis, we present the complete design procedure of a fourth-order single-bit switch-capacitor sigma-delta(Σ-Δ) modulator for audio applications. Recently, oversampling technology is very popular for audio applications, but the fourth-order feedforward(FF) architecture is not applied extensively in Taiwan. Because of the stability problem, the coefficients of high-order architecture of Σ-Δ modulator is very difficult to derive. And it takes a lot of time to simulate in the circuit level. Therefore we present a complete design procedure and use a behavioral model to efficiently reduce the simulation time. So as to reduce the possibility of over-design. In our design, we employ a fully differential opamp and a high-speed, low-power comparator including design guidelines and practical performance considerations, which will be very helpful for someone interested in high-order analog oversampling modulator. The final implementation is a four-order, 320 oversampling ratio, single-bit oversampling modulator in TSMC 2.5V, 0.25μm,1P5M CMOS mixed-mode process. Simulation results reveal that the peak SNDR of 87.1dB can be achieved with a signal bandwidth of 20k Hz and the total power dissipation is 17.7mW for sampling frequency of 12.8M Hz.

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