本篇論文實現一個內建操作頻率為 50 MHz鎖相迴路的數位音頻信號處理器系統。 這個系統具有6個高性能的獨立聲道，主要針對 DVD、家庭劇院和數位電視等音頻信號應用，支援 5.1聲道音頻信號格式。 此格式具有5個全頻域聲道 (5)和1個窄頻聲道 (.1)，為目前市面上廣泛應用的輸入格式。除此之外，本系統可支援字元長度為 16位元至24位元，輸入頻率為 16 kHz 至 192 kHz 的輸入資料。
本系統內建 bass management、bass 和treble 控制器、4頻帶等化濾波器、主僕式音量調整器和主僕式靜音裝置…等數種處理功能。 這些功能可以藉由序列控制介面將我們欲改變的參數輸入至系統中，進而啓動或改變功能特性，達到控制系統的目的。 而且由於採用 30位元資料流和30乘18位元的乘法器架構，部分的內部運算可逹48位元的精確性，因此保有高品質的音頻信號資料。本系統實現於0.35 um互補金氧半製程，面積為 6 x 2.6 mm2，消耗功率小於0.5瓦。系統中的各項功能均已量測並驗証無誤。
此外，本論文亦設計一個電荷幫浦架構的50 MHz輸出時脈鎖相迴路，包含相位 /頻率偵測器、電荷幫浦、迴路濾波器、電壓控制振盪器和除二電路，其中振盪器以環狀架構實現，利用充、放電相等情形使其在控制電壓改變時，輸出責任週期不因頻率變化而大幅改變，在各頻率下均接近50%。 它在本篇的應用主要是拿來作頻率倍增器，重建輸入時鐘信號並提升輸入頻率，供數位音頻信號處理系統使用，實現於 0.25 um 1P5M互補金氧半混合信號製程, 面積為0.4 x 0.4 mm2。

In this thesis, a digital audio signal processor system with a 50 MHz phase-locked loop is designed. This system is a high performance 6-channel, which contains five full range (5) and one band-limited (.1) channels for 5.1-Channel audio. It is designed for audio applications such as DVD, home theater systems, and digital TV. Besides, it supports data input wordlength from 16 to 24-bit and sampling rates from 16 kHz to 192 kHz.
This system contains a number of built-in processing functions including bass management, bass and treble controls; four-band equalizer filters, master and slave volume controllers; master and slave mutes. These functions can be controlled by specifying the desired operating parameters through the serial control interface. The architecture preserves high-quality audio data by using a 30-bit data path, 30 x 18-bit multiplier, and up to 48 bits of precision for some internal calculations. The chip area is 6 x 2.6 mm2 in 0.35 um CMOS process and total power consumption is less than 0.5 W. The system is successfully measured and verified for all functions.
In addition, a 50 MHz charge-pump PLL, which contains phase and frequency detector, charge pump circuit, loop filter, voltage-controlled oscillator and divider, is designed. Ring oscillator is used to generate signal with equal duty-cycle through the electrical character of charging and discharging equally. The duty-cycle is almost 50 % without large variation through frequency changing by controlled-voltage. PLL is used as a frequency multiplier and clock generator for digital audio processor in this system. The chip area is 0.4 x 0.4 mm2 in 0.25 um CMOS 1P5M mixed-signal process.

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