作為四則運算之一，類比除法器至今已被用在許多的應用上。因除法器通常需要與其它電路做結合，與其它電路之相容性對一個除法器來說非常重要。因此，本論文提出一個全新架構之除法器，此除法器能實現兩個電壓之間的除法運算，且將結果直接轉為數位輸出。換句話說，此架構之除法器結合了一個類比除法器以及一個類比數位轉換器 (Analog-to-Digital Converter) 的功能。除此之外，此除法器更可以同時達到高準確度、低功耗以及不受製程變化影響的特性。
本晶片使用台灣積體電路公司0.35μm 2P4M混合訊號製程製作而成，晶片尺寸約為1.25×1.25mm2。本電路之除數輸入電壓範圍為0.1-1V，且被除數之輸入電壓範圍為0.1-1.5V。此外，此電路在3.3V之靜態功耗為205μW、最大功耗為440μW，且其最大誤差小於1.5%。

For being one of the four fundamental arithmetic operations, analog dividers have been utilized in many applications. Since the dividers are usually integrated with other circuits, it is important for dividers to be compatible with other circuits. Therefore, a novel architecture of analog divider is proposed in this thesis. The proposed divider can realize a dividing function of two voltage signals and directly convert the result into digital codes. In other words, it combines the functions of an analog divider and an analog-to-digital converter (ADC). Furthermore, it can achieve high accuracy, low power consumption, and be insensitive to process variation.
The proposed chip was fabricated by TSMC 0.35μm 2P4M CMOS/MEMS mixed-signal process, and the chip size is 1.25×1.25mm2. The input range of the dividend and the divisor is 0.1-1.5V and 0.1-1V, respectively. The maximal error of the proposed divider is lower than 1.5%. Moreover, the quiescent and maximal power consumption is 205μW and 440μW at 3.3V, respectively.

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