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研究生：	劉漢錚 Liu, Han-Zheng
論文名稱：	延遲鎖定迴路之延遲線搜尋研究 Study on Delay Line Search in Delay-Locked Loop
指導教授：	賴源泰 Lai, Yen-Tai
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2011
畢業學年度：	99
語文別：	英文
論文頁數：	60
中文關鍵詞：	延遲鎖定迴路、延遲線搜尋
外文關鍵詞：	Delay-Locked Loop, Delay Line Search
相關次數：	點閱：108 下載：0
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隨著半導體製程技術的快速提升,電路的複雜度及系統執行速度亦隨著快速增加,系統時脈訊號的同步性變的愈來重要,因此許多的技術被提出用以解決時脈抖動及時脈歪斜的問題,如鎖相迴路及延遲鎖定迴路,而因為延遲鎖定迴路在時脈抖動及穩定性上有較佳的表現,因此延遲鎖定迴路被廣為應用於時脈同步方面,而其中又以數位式的架構可達成較快的鎖定時間及具有抗雜訊和不易受製程變化影響等特性。而在本論文中我們提出一種改良式的延遲線搜尋演算法,其目的在於增加延遲線的搜尋效率並同時防止諧波鎖定的情況發生.

本論文採用TSMC 0.18 um製程參數製作,頻率操作範圍為100 - 500 MHz,在最高頻率操作下功率消耗為32mW,操作頻率在500 MHz時方均根抖動量為3.6ps

For the rapid progress in semiconductor process, the circuit complexity and speed of system will also increase. Synchronization of the system clock signal becomes more important. Thus, a lot of technologies such as Delay-Locked Loops (DLLs) and Phase-Locked Loops (PLLs) have been proposed to solve the clock skew and clock jitter issues. Delay-locked loop has been widely applied for clock synchronization because it has the better performance in stability and jitter. The all-digital type DLL has higher noise tolerance 、less impact of process variation and fast locking time than analog type DLL. In this paper, we propose a modified algorithm to improve the delay line search efficiency and to prevent the harmonic locking issue simultaneously.

This work is fabricated in TSMC 0.18μm CMOS process. The operation frequency ranges from 100 MHz to 500 MHz The power consumption is 32 mW and the R.M.S jitter is 3.6ps at 500 MHz .

Abstract
Table of Content
List of Figures
List of Tables
Chapter 1 Introduction	1
1 Motivation	1
2 Clock Skew Issue	2
4 Thesis Overview	3
    
Chapter 2 Delay-Locked Loop	5
1 Delay-Locked Loop Fundamentals	5
2 Phase Detector	7
3 Charge Pump/Loop Filter	8
4 Voltage-Controlled Delay Line	9
4.1 Current Starved Delay Cell	10
4.2 RC time constant controlled delay cell	11
Chapter 3 All Digital Delay-Locked Loop……	12
1 Introduction	12
2 Registered-Controlled DLL	13
3 Counter-Controlled DLL	15
4 Successive Approximation Register-controlled DLL	15
5 Locking Problems	17
5.1 Harmonic Locking	17
5.2 Stuck Locking	18
6 Variable Successive Approximation Register-controlled 
    DLL		19
7 Digital Controlled Delay Line	22
7.1 Coarse Tune Delay Cell	23
7.2 Fine Tune Delay Cell	24
8 Comparisons	27


Chapter 4 Proposed Search Algorithm	29
1 Unnecessary Search Time in Delay Line Search	29
2 Improved Search Algorithm	32
3 Hardware Implementation	35	
3.1 Successive Approximation Register Unit	35
3.2 Selector	36
3.3 Stuck Locking Detection Unit	37
3.4 Fail-to-Lock Judgment	39
3.5 Timing Controller	41
3.6 Digital-Controlled Delay Line	41
3.7 TSPC DFF	44
4 Search Process of proposed algorithm	46

Chapter 5 Experimental Results	50
1 Simulation in SIMULINK	50
2 Simulation in HSPICE	52

Chapter 6 Conclusions	57

References	58

                                    

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