測試成本已成為大型業界電路中的關鍵問題。為了降低測試成本，業界採用了各種測試壓縮技術。選擇適當的輸入及輸出通道數目，能最好地使用測試壓縮技術。本篇論文提出了一種有效方法來估計嵌入式確定性測試(EDT)壓縮技術在不同的壓縮配置下的測試向量數目。為尋找準確估計的方法，我們建立了數學模型來揭示不同壓縮配置之間的關聯。這些模型是基於新穎的理論分析和實際實驗數據建立的。僅根據兩次ATPG運行的結果，就可以獲得對各種壓縮配置的測試向量數目的準確估計。依據9個業界電路的實驗結果，平均向量數目估計錯誤率約 5% 且僅有少數異常值。使用所提出的方法，測試壓縮設計人員可以輕鬆選擇最佳輸入和輸出通道配置以滿足設計需求。

Test cost has become a critical issue for large industrial integrated circuits. To reduce the test cost, various test compression techniques have been adopted in the industry. Appropriate input and output channel counts must be selected to best utilize the test compression technology. This thesis presents an efficient and effective method to estimate the test pattern counts under different compression configurations for the Embedded Deterministic Test (EDT) compression technique. In searching for the accurate estimation method, we build mathematical models that reveal the internal relationship among different compression configurations. The models are established based on novel theoretical analysis as well as actual experimental data. Accurate estimation of test pattern counts for a wide range of compression configurations can be obtained based on the results of only two ATPG runs. Experimental results on 9 industrial circuits show that the average pattern count estimation error rate is about 5% with very few outliers. With the proposed method, a test compression designer can easily pick the best input and output channel configuration to fit the design needs.

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