在現今半導體製程的技術下，一個完整的電路系統內的所有組成的電路元件幾乎都可以被整合進單晶片系統。由於處理器的電路日益複雜，導致處理器測試難度增高，故在單晶片系統內的嵌入式處理器測試上變得更困難。傳統上以掃描鍊為基礎的測試架構，將會造成硬體電路、測試成本的增加與電路效能的降低。因此軟體測試方式幾乎不對硬體電路和測試成本產生影響的特性，則提供嵌入式處理器一另個選擇來有效解決以上問題。
在此論文中，我們提出一個嵌入式處理器的軟體測試方法。此軟體測試方法主要根據處理器的指令集與管線架構來產生測試程式。在此方式之下的特點不僅不會為了電路的可測試性而改變處理器的原始電路設計，而且只利用處理器的架構與所使用的指令集來對其內部所組成的電路元件做測試。我們不需要知道gate-level的資訊就可產生測試程式，且利用這個測試程式我們能達到不錯的fault coverage。
為了驗證該測試方法的效果，我們用ERM9處理器作為測試樣本。ERM9(增強型精簡指令運算處理器)是以ARMv4T的指令集來設計。實驗結果顯示此為一個可行的方式來解決嵌入式處理器測試問題。

With rapidly advanced semiconductor manufacturing technology, almost all components of a complete system can be integrated into a system-on-chip (SOC) today. However, the poor controllability and observability of processors make the testing of SOC more and more difficult. Traditional scan-based test architectures applied to an embedded processor result in hardware overhead, and performance degradation. Therefore, software-based testing for embedded processors has been proposed as an effective alternative.
In this thesis, we propose a software-based test methodology that generates an effective test program according to the instruction set architecture and the pipeline architecture of the processor. The advantages of this test methodology are its non-intrusive nature and its capability to use the processor resources and the instruction set to test components of the processor. This test program is generated without knowing gate-level information, and can achieve high fault coverage. To verify the practicability of the method, we use an ERM9 (Enhanced RISC Machine) processor as a benchmark. The ERM9 is designed using the ARMv4 instruction set and 5-stage pipeline architecture. Experimental results show that the proposed method achieves high test efficiency on processor testing.

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