在本論文中，主要實現一個可操作在1GHz十位元的電流導向式數位類比轉換器，並且探討它的設計分法及設計時所需要注意的地方。這個設計使用台積電(TSMC) 1P6M 0.18m CMOS數位製程來實現。在此架構中，其中最大的6個數位碼轉成溫度碼，最小位元的4個碼使用二進位碼。為了更容易和數位系統整合，在此電路架構中的類比電路的電源電壓為與數位電路相同的1.8V.。我們也使用管線 (Pipeline) 式架構來設計數位解碼器以符合高速度操作的需求。同時，為了達到所需要的靜態和動態特性，我門使用了很多技巧，例如：電流源電晶體滿足靜態線性的需求，電流源電晶體開關的切換計畫，電路佈局的最佳化，防止電源線互相耦合的技巧等，去改善電路效能。

　　當電路操作在500MHz的頻率，輸入旋波訊號在200MHz時，電路的無雜訊動態範圍(SFDR)可達到62dB；當電路操作頻率達到1G時，輸入旋波訊號達到100MHz時，電路的 SFDR可達到至少55dB的要求。電路的靜態特性也有不錯的表現，其中最具代表性的差分非線性誤差(DNL)和積分非線性誤差(INL)，分別小於0.1LSB和0.15LSB。當電路操作在1GHz的頻率，輸入旋波訊號為100MHz，電路只消耗35mW的功率，整個晶片核心的面積只有0.5mm2，整體晶片面積為1.21mm2。

　In this thesis, a 10-bit 1-GSample/s segmented digital-to-analog converter is proposed. It is implemented in TSMC standard 0.18m 1P6M CMOS technology. The segmented architecture of this current steering DAC consists of 6bit MSB that is constructed by thermometer code structure and 4bit LSB that is binary weighted one. To be easier intergraded in the digital system, the power supply in the analog part is designed in1.8V. To achieve high speed, we use pipeline architecture in the thermometer decoder to alleviate their speed requirement. To improve static and dynamic specifications, many issues, such as INL yield requirement, switching scheme, layout optimization and power lines decoupling, in designing this DAC are taken care of.

　For a 500MHz update rate, the SFDR is 62dB at 200MHz signal frequency. When the update rate reaches to 1GHz, the SFDR is 55dB at 100 MHz signal frequency. The DNL is less than 0.1 LSB, and the INL is less than 0.15 LSB. The power consumption is 35mw at a 100MHz input signal with 1GHz update rate. The active area is 0.5mm2 and the total area is 1.21mm2.

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