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研究生： 馬兆賢
Ma, Chao-Hsien
論文名稱： 一個利用殘值超取樣及自我偏壓技術的十二位元每秒取樣四百萬次之雙模式連續漸進逼近式類比數位轉換器
A 12-bit 4-MS/s Dual-Mode SAR ADC with Self-Biased Switching and Residue Oversampling Techniques
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2020
畢業學年度： 108
語文別： 英文
論文頁數： 106
中文關鍵詞： 逐漸趨近式 、類比數位轉換器 、動態元件匹配 、高解析 、超取樣 、殘值超取樣 、自我偏壓
外文關鍵詞： Successive approximation register (SAR) analog-to-digital converter (ADC), Dynamic Element Matching, High-resolution, Oversampling, Residue Oversampling, Self-Biased
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    • 本論文提出一個高解析度之十二位元每秒取樣四百萬次之雙模式連續漸進逼近式類比數位轉換器。
    此類比數位轉換器結合了殘值超取樣的架構與本論文所提出的自我偏壓技術。所提出之自我偏壓技術能透過進入比較前的切換方式來產生在單端模式下所需要的比較基準點，並且可隨著參考電壓改變而跟著準確地改變。另外，殘值超取樣技術利用交換電容陣列搭配動態元件匹配技術對殘值電壓進行重複解析，並將殘值的輸出碼平均以得到更精確的數位碼。以此，在不需校正的情況下，能降低電容不匹配所產生的影響以及提升類比數位轉換器的精確度。
    本論文以華力微28奈米製程研製一個十二位元的逐漸趨近式類比數位轉換器，核心電路面積為0.0665mm2。當晶片操作在0.9伏特的電壓供應下與400萬赫茲(4-MS/s)的取樣頻率時，模擬效能顯示，在奈奎斯特(Nyquist-rate)輸入頻率下，雙端模式可以達到有效位元為 11.70 位元(SNDR為 72.19 dB)，單端模式可達到有效位元為10.70位元(SNDR 為 66.17 dB )。

    This thesis presents a high-resolution 12-bit 4-MS/s dual-mode successive-approximation register (SAR) analog-to-digital converter (ADC).
    This SAR ADC adopts proposed Self-Biased Switching and Residue Oversampling techniques. With the proposed Self-Biased Switching, the comparison reference of single-ended mode could be generated before conversion. Besides, this method aligns this comparison reference with Vref enlarged. For Residue Oversampling, by repeating the residue voltage conversion and combining Dynamic Element Matching, roles of capacitors are rearranged to generate different residue voltages. Residue voltages output codes are averaged to generate a high-precision digital code. By this technique, the capacitor mismatch is reduced and accuracy of the ADC is improved without calibration.
    The proof-of-concept 12-bit SAR ADC was fabricated in a HLMC 28-nm CMOS technology, of which the core circuits occupy an area of 0.0665mm2. As the prototype operates at a supply voltage of 0.9 -V and sampling rate of 4-MS/s, the simulation results show that the prototype ADC achieves 72.19 dB and 66.17 dB SNDR with a Nyquist-rate input in differential and single-ended modes, respectively.

    摘　要 I Abstract III List of Tables VIII List of Figures IX List of Abbreviations XIII Chapter 1 Introduction 1 1.1 Background and Motivation 1 1.2 Thesis Organization 4 Chapter 2 Fundamentals of Analog-to-Digital Converters 5 2.1 Analog to Digital Converter 5 2.2 Quantization Error, Resolution, and Accuracy 6 2.2.1 Quantization Error 7 2.2.2 Resolution 8 2.2.3 Accuracy 9 2.3 Static Specification 10 2.3.1 Offset Error 10 2.3.2 Gain Error 11 2.3.3 Nonlinearity 12 2.4 Dynamic Specification 16 2.4.1 Signal-to-Noise Ratio (SNR) 16 2.4.2 Signal-to-Noise and Distortion Ratio (SNDR) 18 2.4.3 Effective Number of Bits (ENOB) 18 2.4.4 Spurious-Free Dynamic Range (SFDR) 18 2.4.5 Total Harmonic Distortion (THD) 19 2.4.6 Effective Resolution Bandwidth (ERBW) 21 2.4.7 Figure of Merit (FoM) 21 Chapter 3 Introduction of High-Resolution SAR ADC 22 3.1 The Basic of SAR ADC 22 3.1.1 The Concept of SAR ADC 23 3.1.2 Circuit Operation of the SAR ADC Architecture 25 3.2 Performance Limitations of High-Resolution SAR ADCs 28 3.3 Oversampling 32 3.4 Techniques for Nyquist-Rate ADCs 36 3.4.1 Detect-and-Skip Algorithm 36 3.4.2 Correlated-Reversed Switching Technique 38 3.4.3 Majority-Voting Technique 39 3.4.4 Adaptive-Averaging Technique 40 3.4.5 Pipeline SAR ADC 42 Chapter 4 A 12-bit 4-MS/s SAR ADC 45 4.1 Techniques Adopted 46 4.1.1 Self-Biased Switching 46 4.1.2 Residue Oversampling 56 4.2 Architecture of the proposed SAR ADC 63 4.2.1 Simplified-DEM Structure 64 4.2.2 Error-Tolerance Range 66 4.2.3 Architecture 67 4.2.4 Capacitor Switching Methods 71 4.3 Behavior-model Simulations 74 4.3.1 Behavior-model Simulations with SBS 75 4.3.2 Behavior-model Simulations with Noise 76 4.3.3 Behavior-model Simulations with Capacitor Mismatch 78 4.4 Circuit Implementation 79 4.4.1 Bootstrapped Switch 79 4.4.2 Dynamic Two-Stage Comparator 81 4.4.3 Digital Error Correction Decoder 84 4.4.4 Capacitive DAC 86 Chapter 5 Layout and Simulation Results 90 5.1 Layout and Chip Floor Plan 90 5.2 Simulation Results 93 Chapter 6 Conclusions and Future Works 100 Bibliography 102

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