在本論文中，我們提出一應用於系統晶片(SOC)中，高速萬用內建式記憶體自我測試電路架構(Universal Memory BIST Architecture)，對於系統晶片中大量及不同形式的記憶體，我們提出一新的編碼方式，可大量減少實體信號產生電路的複雜度，及增加記憶體的測試效率，使用者僅需自記憶體使用手冊(Memory Specifications)取出數個參數(Parameters)，透過這些參數，控制電路即可產生此種記憶體相應的控制時序 。
　　對各種不同形式的記憶體，所採用之Fault Model亦有不同，為了達到最高的Fault Coverage及測試效率，本架整合了42種March Algorithms，透過對March Elements的化簡，利用8個Dominate Steps即可代表258種March Elements，可大幅減少演算法儲存的空間，使用者僅需簡單的設定，即可決定希望採用的March Algorithm。

　　In this Thesis, we propose a high speed universal memory BIST architecture for the heterogeneous embedded memory cores in SOCs. A novel encoding scheme is proposed for our architecture to reduce the complexity and improve the test efficiency of physical signal control circuitry with different types of memories. The physical control signals are generated according to the parameters provided by the users from memory specifications. Besides, the proposed architecture realizes 42 March algorithms. It supports different types of memories that have different fault models.

[1] A. J. van de Goor and A. Offerman, “Towards a Uniform Notation for Memory Tests,” Proc. of European Design and Test Conf., 1996, pp. 420-427.

[2] A. J. Van De Goor,” Using march tests to test SRAMs,” Design & Test of Computers, IEEE, March 1993, pp.8 – 14.

[3] V. G. Mikitjuk, V. N. Yarmolik, and A.J. van de Goor, “RAM Testing Algorithms for Detecting Multiple Linked Faults,” Proc. of European Design and Test Conf., 1996, pp. 435-439.

[4] P. Camurati, P. Prinetto, M. S. Reorda, S. Barbagallo, A. Burri, D. Medina, “Industrial BIST of embedded RAMs,” Design & Test of Computers, IEEE , 1995, pp.86.

[5] S. Park, K. Lee, C. Im, N. Kwak, K. Kim, Y. Choi, ”Designing built-in self-test circuits for embedded memories test,” Proceedings of the Second IEEE Asia Pacific Conference, Aug. 2000 , pp.315 – 318.

[6] C. T. Huang; J. R. Huang; C. F. Wu; C. W. Wu; T. Y. Chang, “A programmable BIST core for embedded DRAM,” Design & Test of Computers, IEEE , Jan.-March 1999, pp.59 – 70

[7] M. Zhang, D. Tao, B. Wei,” A programmable BIST for embedded SDRAM,” VLSI Technology, Systems, and Applications, 2001. Proceedings of Technical Papers. 2001 International Symposium on , 18-20 April 2001, pp.244 – 248.

[8] A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto, M. Lobetti Bodoni, “A programmable BIST architecture for clusters of multiple-port SRAMs, ”Test Conference, 2000. Proceedings. International , 3-5 Oct. 2000, pp.:557 – 566.

[9] A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto, M. L. Bodoni, ”Programmable built-in self-testing of embedded RAM clusters in system-on-chip architectures,” Communications Magazine, IEEE, Sept. 2003, pp.90 – 97.

[10] C. H. Tsai; C. W. Wu, ”Processor-programmable memory BIST for bus-connected embedded memories,” Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific , 30 Jan.-2 Feb. 2001 , pp.325 – 330.

[11] B. Zeidman, “Verilog Designer’s Library,” Prentice Hall.

[12] Free IP: SDRAM Controller, http://www.cmosexod.com/sdram.html.

[13] Altera Free IP: DRAM Controller, http://www2.cic.org.tw/~steven/download/ ip/dynram.html

[14] W. L. Wang, K. J. Lee, and J. F. Wang, “An On-Chip March Pattern Generator For Testing Embedded Memory Cores”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 9, No. 5, Oct. 2001, pp. 730-735.

[15] W. L. Wang, K. J. Lee, and J. F. Wang, “A Universal March Pattern Generator for Testing Embedded Memory Cores”, Proceedings of 12th Annual IEEE ASIC/SOC Conference, 1999, pp. 228-232.

[16] W. L. Wang, K. J. Lee and J. F. Wang, “An Embedded March algorithm Test Pattern Generator for Memory Testing,” Proceedings of International Symposium on VLSI Technology, Systems, and Applications, 1999, pp. 211–214.

[17] V. Yarmolik, Y. Klimets, and S. Demidenko, "March PS (23N) Test for DRAM Pattern-Sensitive Faults," Proc. of 7th Asian Test Symp., Singapore, December 1998, pp. 354-357.

[18] A. J. van de Goor and G. N. Gaydadjiev, “March U: A Test for Unlinked Memory Faults,” IEE Proc. - Circuits Devices Syst., Vol. 144, No. 3, June 1997, pp. 155-160.

[19] A. J. van de Goor, G. N. Gaydadjiev, V. N. Yarmolik, and V. G. Mikitjuk, “March LR: A Test for Realistic Linked Faults,” Proc. of European Design and Test Conf., 1997, p. 627.

[20] A. J. van de Goor, G. N. Gaydadjiev, V. N. Yarmolik, and V. G. Mikitjuk, “March LR: A Test for Realistic Linked Faults,” Proc. of 14th VLSI Test Symposium, 1996, pp. 272-280.

[21] Micron Technology memory simulation models, http://www.micron.com.

[22] N. H. Tseng, “Universal BIST for Heterogeneous Embedded Synchronous Memory cores in SOC”, Master Thesis, Dept. of E.E., NCKU, Taiwan, June, 2002.

[23] Cypress Technology memory simulation models, http://www.cypress.com.

[24] Samsung Technology memory simulation models, http://www.samsung.com.

[25] K. L. Cheng, C. M. Hsueh, J. R. Huang, J. C. Yeh, C. T. Huang, C. W. Wu, ”Automatic generation of memory built-in self-test cores for system-on-chip,” Test Symposium, 2001. Proceedings. 10th Asian , 19-21 Nov. 2001, pp.91 – 96.

[26] C. Cheng, C. T. Huang, J. R. Huang, C. W. Wu, C. J. Wey, M. C. Tsai, ”BRAINS: a BIST compiler for embedded memories,” Defect and Fault Tolerance in VLSI Systems, 2000. Proceedings. IEEE International Symposium, 25-27 Oct. 2000, pp.299 – 307.