本論文分為兩大部分，第一部分是研製應用於802.11a WLAN接收機之5.7GHz CMOS差動低雜訊放大器及雙平衡式混波器RFIC。第二部分是研製應用於數位電視射頻調諧器的CMOS射頻前端(75Ω系統)RFIC，包括寬頻可調增益差動低雜訊放大器及寬頻雙平衡式混波器。研製之RFIC均使用TSMC 0.18μm 1P6M CMOS製程，晶片量測皆採用打鎊線至PCB測試板上進行。
　　5.7GHz可調增益差動低雜訊放大器量測所得增益可由11.8dB調整至0dB，雜訊指數小於4.5dB，input P1dB為-14dBm；雙平衡混波器量測所得轉換損耗為8.6dB，雜訊指數為14.3dB，input P1dB為3dBm。
數位電視射頻調諧器的40~900MHz寬頻可調增益差動低雜訊放大器，在輸入及輸出使用50轉75Ω之阻抗轉換衰減器及平衡器以轉換成50Ω單端系統來量測。論文介紹兩種不同調整增益方式設計之LNA RFIC，以改變源極退化(source degeneration)來調整增益並增加線性度LNA電路的設計量測結果為；增益可由20.8±1.6調整至-15.5±2.8dB，雜訊指數小於4.5dB，input P1dB@high-/low-gain mode為-19.8~-22.7/-11~-13.6dBm。寬頻雙平衡混波器量測結果為，轉換損耗為2.8±1dB，雜訊指數為12.9~16.7dB，input P1dB為-1.9~-3.8dBm。要注意的是，混波器為考量到下一級之SAW filter之輸入阻抗，而將IF輸出阻抗設計為200Ω；但量測儀器為50Ω單端系統，故在混波器IF端接上balun來量測，與模擬相比較，推斷轉換增益若在真正的使用環境下(200Ω IF-load)可能會提高約6dB左右。整合低雜訊放大器及混波器為單一晶片之40~900MHz射頻前端RFIC的量測結果為，增益約17.5±2.9dB(with 50ΩIF-load)，雜訊指數小於6.7dB，input P1dB 約-24~-20.6dBm。16QAM OFDM數位調變之量測結果為，EVM = 0.8/0.7/0.7% @ 40/500/900MHz，靈敏度約為-90.7dBm(@code-rate=1/2)及 -85.6dBm(@code-rate=7/8)。
　　另外本論文設計之一全積體化2.4/5.7GHz同時共用雙頻帶CMOS差動低雜訊放大器及一5.7GHz WLAN CMOS射頻接收機晶片(包括低雜訊放大器、混波器、頻率合成器)的模擬結果置於附錄中。

　　This thesis presents the research on differential CMOS RFICs for the 5GHz 802.11a WLAN receiver and DTV RF tuner applications. The RFICs are fabricated by a TSMC standard 0.18μm CMOS process. The circuit measurement is performed using a FR-4 PCB test fixture. The 5GHz receiver CMOS RF front-end includes a differential LNA with gain control and a double-balanced mixer. The RF (5.725 to 5.825 GHz) is downconverted to a 480 MHz IF. The LNA exhibits a gain of 11.8dB, noise figure less than 4.5dB, input P1dB of -14dBm, and gain tuning range of 11.8 dB. The power consumption is 19.8 mW at VDD = 1.8 V. The mixer exhibits a conversion loss of 8.6dB, noise figure of 14.3dB, and input P1dB of 3dBm. The power consumption is 5.4 mW at VDD = 1.8 V.
　　The broadband CMOS differential RFIC for the DTV tuner RF front-end includes a broadband differential LNA (BDLNA) with gain control and a broadband double-balanced mixer. The RF frequency to the DTV tuner ranging from 40 to 900MHz is up-converted to a 1220MHz 1st IF. The BDLNA (40 to 900MHz) is designed with 75Ω/75Ω differential input/output impedance and exhibits a gain of 20.8±1.6dB, noise figure less than 4.5dB, input P1dB@high-/low-gain mode of -19.8~ -22.7/-11~-13.6dBm, and gain tuning range of about 36 dB. The power consumption is 43.2 mW at VDD = 1.8 V. The broadband mixer exhibits a conversion loss of 2.8±1dB, noise figure of 12.9~16.7dB and input P1dB of -1.9~-3.8dBm. The power consumption is 7.2 mW at VDD = 1.8 V. It is noted that the IF output is designed with a 200Ω load to accommodate the input impedance of the IF SAW filter. Since the measurement is performed with a 50Ω system, compared with the simulation result, the conversion gain of the mixer may increase for about 6 dB when connected to a 200Ω IF load. The integrated RF front-end chip exhibits a conversion gain of 17.5±2.9dB, noise figure less than 6.7dB, input P1dB of -24~-20.6dBm. As indicated, the conversion gain may increase for about 6 dB when the chip is connected to a 200Ω IF load. With a 16-QAM emulated WLAN OFDM digital signal (data rate=36Mbps, BW=20MHz), the measured EVM is 0.8/0.7/0.7% @ 40/500/900MHz, respectively. From the measured EVM values, the sensitivity is determined to be about -90.7dBm (@code-rate=1/2) and -85.6dBm (@code-rate=7/8).

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