本文應用場規畫邏輯閘陣列(Field Programmable Gate Array; FPGA)於數位單相功率因數修正器之研製。文中所設計的功因修正器係將類比控制電路製作成數位IC，並使用分散式算術演算法以大幅減少FPGA內部邏輯方塊的需求，及降低控制電路成本。另本文在輸出電壓取樣方面，採用電壓零點取樣法，使輸出電壓側產生一虛擬凹陷式濾波器的功能，以替代原有之低通濾波器，因而使得負載在激烈的變動下，仍能快速將輸出電壓穩定控制在設定值。本文由數位模擬結果與硬體電路實作，證實依本文所提之方法在功因修正器之研製上、確實具有提高功因與降低成本及快速穩定輸出電壓之功能。

In this thesis, the implementation of single-phase power factor corrector has been effectively achieved with the aid of field programmable gate array (FPGA). By using the distributed arithmetic method, the number of configurable logic cells inside the FPGA can be reduced, facilitating the reduction of development cost. Besides, for the issue of output voltage sampling, a zero-point voltage sampling approach has been adopted in this thesis. With this strategy, the output voltage side can generate a equivalently virtual notch filter in order to replace the low-pass filter while the voltage can be thus better maintained at the predetermined value along with a fast response even under a drastic load variation. This proposed method has been validated through the software simulations and hardware implementation. Test results solidify the feasibility of the proposed method in both power factor improvement and voltage stabilization.

[1] Q. Zhao, F. Tao, P. Xu, J. Wei and F. C. Lee, “Improving performance of continuous current mode boost converters for power factor correction,” Proceedings of Power Electronics Specialists Conference, Vancouver, Canada, June 2001, pp. 642-647.

[2] C. K. Tse and M. H. L. Chow, “Theoretical study of switching power converters with power factor correction and output regulation,” IEEE Transactions on Circuits and Systems, Vol. 47, No. 7, July 2000, pp. 1047-1055.

[3] N. P. Papanikolaou and C. E. Tatakis, “Minimisation of power losses in PFC flyback converters operating in the continuous conduction mode,” IEE Proceedings- Electric Power Applications, Vol. 149, No. 4, July 2002, pp 283-291.

[4] Q. Zhao, F. Tao, F. C. Li, P. Xu and J. Wei, “A simple and effective method to alleviate the rectifier reverse-recovery problem in continuous-current-mode boost converters,” IEEE Transactions on Power Electronics, Vol. 16, No. 5, September 2001, pp. 649-658.

[5] M. H. L, Chow, K.W. Siu, C.K. Tse and Y. S. Lee, “A novel method for elimination of line-current harmonics in single-stage PFC switching regulators,” IEEE Transactions on Power Electronics, Vol. 13, No. 1, January 1998, pp. 75-83.

[6] Y. K. E. Ho, S. T. R. Hui and Y. S. Lee, “Characterization of single-stage three-phase power-factor-correction circuit using modular single-phase PWM DC-to-DC converters,” IEEE Transactions on Power Electronics, Vol. 15, No. 1, January 2000, pp. 62-71.

[7] C. S. Moo, H. C. Yen, Y. C. Hsieh and Y. C. Chuang, “Integrated design of EMI filter and PFC low-pass filter for power electronic converters,” IEE Proceedings- Electric Power Applications, Vol. 150, No. 1, January 2003, pp. 39-44.

[8] V. Grigore, J. Kyyra and J. Bajamaki, “Input filter design for power factor correction converters operating in discontinuous conduction mode,” 1999 IEEE International Symposium on Electromagnetic Compatibility, Seattle, WA , USA, August 1999.Vol. 1, pp. 145-150.

[9] A. C. Wang and S. R. Sanders, “Programmed pulsewidth modulated waveforms for electromagnetic interference mitigation in DC-DC converters,” IEEE Transactions on Power Electronics, Vol. 8, No. 4, October 1993, pp. 596-605.

[10] M. Vilathgamuwa, J. Deng and K. J. Tseng, “EMI suppression with switching frequency modulated DC-DC converters,” IEEE Industry Applications Magazine ,Vol. 5, No. 6, November/December 1999, pp. 27-33.

[11] J. Qian and F. C. Y. Lee, “A high-efficiency single-stage single-switch high-power-factor AC/DC converter with universal input,” IEEE Transactions on Power Electronics, Vol. 13, No. 4, July 1998, pp. 699-705.

[12] Z. Lai and K. M. Smedley, “A family of continuous-conduction-mode power-factor-correction controllers based on the general pulse-width modulator, ” IEEE Transactions on Power Electronics, Vol. 13, No. 3, May 1998, pp. 501-510.

[13] J. Rajagopalan, F. C. Lee and P. Nora, “A general technique for derivation of average current mode control laws for single-phase power-factor-correction circuits without input voltage sensing,” IEEE Transactions on Power Electronics, Vol.14, No. 4, July 1999, pp. 663-672.

[14] M. Magao, “A novel one-stage forward-type power-factor-correction circuit,” IEEE Transactions on Power Electronics, Vol. 15, No. 1, January 2000, pp. 103-110.

[15] J. Hahn, P. N. Enjeti and I. J. Pitel, “A new three-phase power factor correction (PFC) scheme using two single-phase PFC modules,” IEEE Transactions on Industry Applications, Vol. 38, No. 1, June 2002, pp. 123-130.

[16] M. Qiu, G. Moschopoulos, H. Pinheriro and P. Jain, “A PWM full-bridge converter with natural input power factor correction,” 29th Annual IEEE Power Electronics Specialists Conference, Fukuoka , Japan, pp. 1605-1611.

[17] P. J. Villegas, J. Sebastian, M. M. Hernando, F. Nuno and J. A. Martinze, “Average current mode control of series-switched post-regulators used in power factor correctors, ” 29th Annual IEEE Power Electronics Specialists Conference, Fukuoka , Japan, pp. 1808-1814.

[18] L. Ping, M. Yu, K. Yong, Z. Hui and C. Jian, “Analysis of single-phase boost power factor correction (PFC) converter,” Proceedings of the IEEE 1999 International Conference on Power Electronics and Drive Systems, Hong Kong, pp. 933-937.

[19] D. Xu, J. Zhang, W. Chen, J. Lin and F. C. Lee, “Evaluation of output filter capacitor current ripples in single phase PFC converters, ” Proceedings of the Power Conversion Conference, Osaka, Japan, April 2002, pp. 1226-1231.

[20] S. L. Jung, M. Y. Chang, J. Y. Jyang, H. S. Huang, L. C. Yeh and Y. Y. Tzou, “Design and implementation of an FPGA-based control IC for the single-phase PWM inverter used in an UPS,” 1997 International Conference on Power Electronics and Drive Systems, Singapore, May 1997, pp. 344-349.

[21] S. L. Jung, M. Y. Chang, J. Y. Jyang L. C. Yeh and Y. Y. Tzou, “Design and implementation of an FPGA-based control IC for AC-voltage regulation,” IEEE Transactions on Power Electronics, Vol. 14, No. 3, May 1999, pp. 522-532.

[22] S. L. Jung, M. Y. Chang, J. Y. Jyang, H. S. Huang, L. C. Yeh and Y. Y. Tzou, “Design and implementation of an FPGA-based control IC for the single-phase PWM inverter used in an UPS,” International Conference on Power Electronics and Drive Systems, Singapore, May 1997, pp. 344-349.

[23] N. Mohan, T. M. Undeland and W. P. Robbings, Power electronics converter applications and design, JOHN WILEY & SONG, INC., New York, USA, 1995.

[24] 梁適安, “交換式電源供給器之理論與實務設計,” 全華科技圖書股份有限公司, 民國90年.

[25] P. N. Wood, “Flourescent ballast design using passive PFC and crest factor control,” The 1998 IEEE Industry Applications Conference, St. Louis, MO, USA, October 1998, pp. 2076-2081.

[26] R. Zhang and F. Z. Lee, “Optimum PWM pattern for a three-phase boost DCM PFC rectifier,” Twelfth Annual Applied Power Electronics Conference and Exposition, Atlanta, GA , USA, February 1997, pp. 895-901.

[27] J. C. Crebier, P. Barbosa, F. Canales, F. C. Lee and J. P. Ferrieux, “Frequency domain analysis and evaluation of differential mode input current for three-phase DCM boost rectifiers with different control strategies,” 2000 IEEE 31st Annual Power Electronics Specialists Conference, June 2000, pp. 482-487.

[28] B. R. Lin and H. H. Lu, “Single-phase power-factor-correction AC/DC converters with three PWM control schemes,” IEEE Transactions on Aerospace and Electronic Systems, Vol. 36, No. 1, January 2000, pp. 189-200.

[29] Y. Qin and S. Du, “A novel adaptive hysteresis band current control using a DSP for a power factor corrected on-line UPS,” New Orleans, LA , USA, November 1997, pp. 208-212.

[30] A. Hirota, S. Nagai, M. A. AI, M. Rukonuzzaman and Nakaoka, “A novel hysteresis current control scheme for single switch type single phase PFC converter,” Proceedings of the Power Conversion Conference, Osaka, Japan, April 2002, pp. 1223-1225.

[31] B. R. Lin, D. P. Wu and T. F. Shiue, “Three-phase PFC with space vector and hysteresis control methods,” 1997 International Conference on Power Electronics and Drive Systems, Singapore, May 1997, pp. 48-52.

[32] C. Zhou, R. B. Ridley and F. C. Lee, “Design and analysis of a hysteretic boost power factor correction circuit,” 21st Annual IEEE Power Electronics Specialists Conference, San Antonio, TX, USA, June 1990, pp. 800-807.

[33] R. Wu, S. B. Dewan and G. R. Slemon, “A PWM AC-to-DC converter with fixed switching frequency,” IEEE Transactions on Industry Applications, Vol. 26, No. 5, September/October 1990, pp. 880-885.

[34] J. M. S. Kim, P. Shankar and W. Zhang, “Analysis of predictive control for active power factor correction,” 20th International Conference on Industrial Electronics, Bologna, Italy, September 1994, pp. 446-451.

[35] P. Ninkovic and Z. Janda, “Minimum Settling Time Voltage Regulation of Single-Phase PFC Converters,” The 8th IEEE International Conference on Electronics, Circuits and Systems, Spain, September 2001, pp. 149-152.

[36] J. Zhou, Z. Lu, Z. Lin, Y. Ren, Z. Qian and Y. Wang, “Novel Sampling Algorithm for DSP Controlled 2 kW PFC Converter,” IEEE Transactions on Power Electronics, Vol. 16, No. 2, March 2001, pp. 217-222.

[37] http://direct.xilinx.com/bvdocs/publications/ds001_1.pdf

[38] http://direct.xilinx.com/bvdocs/publications/ds001_2.pdf

[39] http://direct.xilinx.com/bvdocs/publications/ds001_3.pdf

[40] http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Spartan-II

[41] H. C. Karathanasis, “A Low ROM Distributed Arithmetic Implementation of the Forward/Inverse DCT/DST Using Rotations,” IEEE Transactions on Consumer Electronics, Vol. 41, No. 2, May 1995, pp.263-272.

[42] G. Martinelli, R. L. Prina, and S. Ragazzini, “Distributed Arithmetic Perceptron,” IEE Proceedings- Circuit, Devices and Systems, Vol.141, No. 5, October 1994, pp. 382-386.

[43] V. Bochev, “Distributed Arithmetic Implementation of Artificial Neural Networks,” IEEE Transactions on Signal Processing, Vol. 41, No. 5, May 1993, pp. 2010-2013.

[44] A. Berkeman, V. Owall and M. Torkelson, “A low logic depth complex multiplier using distributed arithmetic,” IEEE Journal of Solid-State Circuits, Vol. 35, No. 4, April 2000, pp. 656-659.