在生醫訊號擷取系統中，類比數位轉換器擔任將類比訊號轉換成數位訊號的重要角色。本研究採用連續趨近式類比數位轉換器的架構，由於其具有低功耗、中等轉換速度與高解析度的特點，適合生醫訊號的應用，而其架構由取樣保持電路、比較器、連續趨近式暫存器控制邏輯閘、數位類比轉換電容陣列與輸出暫存器所組成。在此為達到12位元解析度，以雙端差動對輸入的架構實現，並採用有效能量開關切換的方式來降低功耗，並且改變其切換方式，使得數位類比轉換器電容陣列之輸出能夠往共模準位電壓作逼近，以降低比較器偏移之變化。在生醫系統操作中，為了使所提出的連續趨近式類比數位轉換器能符合多種生醫訊號使用，在此設計可調的功能，使其亦能操作在8位元的解析度下。另外，為了避免在8位元操作時浪費多餘的功耗，只切換八位元所須之電容陣列與邏輯閘來做改善。晶片使用台積電0.18微米1P6M製程實現，供應電壓為1.8伏特，取樣頻率為200千赫茲。在輸入頻率10千赫茲下，由實際量測結果顯示，訊號與雜訊失真比為65.69分貝，有效位元數為10.62位元，晶片核心面積為0.904*0.65平方毫米。

An analog-to-digital converter (ADC) plays an important role to transfer analog signals to digital codes for a biomedical acquisition system due to its characteristics of low power consumption, medium speed and high resolution. A successive approximation analog-to-digital converter (SA ADC) is composed of a sample-and-hold (S/H) circuit, a comparator, a successive approximation register (SAR) control logic, capacitor array of digital-to-analog converter (DAC) and an output register. The fully differential architecture and energy-efficient switching scheme are adopted to achieve 12-bit resolution and reduce the power consumption, respectively. Switching operation is modified to make the output voltage of the capacitor array of the DAC to approach the common mode voltage, Vcm, for reducing the variation of comparator offset voltage. For various biomedical signal applications, an adaptive resolution ADC is designed to operate not only in 12-bit but also in 8-bit resolution. The proposed SA ADC also improves the power consumption in 8-bit operation. The proposed ADC was implemented in TSMC 0.18-µm CMOS process. The measurement results show that SNDR is 65.59 dB and ENOB is 10.62 bits at 1.8 V supply voltage. The core area of the chip is 0.904*0.65 mm^2.

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