在一般傳統快速鎖定頻率合成器中，鎖定時間大約落在幾個微秒附近，對於UWB系統來說，仍舊無法滿足需求。因此目前要符合UWB要求之頻率合成器架構大概可分為兩種，第一就是使用多個鎖相迴路與除頻器來產生所需的頻帶;另一種利用兩個或更少的鎖相迴路產生鎖定之頻率再搭配除頻器、混頻器與多工器來產生所有的頻帶，但此種方法系統往往較為複雜，對於整個系統來說，仍舊占了相當部分的面積與功率消耗。因此在本研究，將嘗試使用一種設計技巧來簡化電路的複雜度，並實現快速切換之頻率合成器，若實際量測可行，預計將可以推廣至完整頻段之UWB系統。實驗室之前提出一種跳頻鎖定之方法，藉由VCO與除頻器的適當控制，能讓不同頻段切換時消耗非常少的時間。
在本論文中我們將使用跳頻鎖定的方法，使得切換加上鎖定的時間能夠小於10奈秒，符合了運用在UWB系統上。而我們就藉著此種技術來實作一個運用在UWB mode-1頻帶的鎖相迴路。在VCO部分我們做到了3.432、3.96以及4.488GHz等頻率的切換，其相位雜訊各為-120.1、-119.4及-120.7dBc/Hz。在電荷幫浦的電流設計大約為150微安培，預估製程變異大約+-5％，在模擬中我們把vctrl的部分設計在0.5~1.3V之間是可被接受的。在最後整個的PLL模擬中可看出鎖定時間小於10奈秒，也正符合了UWB系統的需求。
此論文大致上分為三個部分，第一部份介紹了UWB的技術背景以及其應用同時也闡明本論文之研究動機，第二部份探討鎖相迴路的基本架構，包含了相位檢測器、電流幫浦、低通濾波器、壓控振盪器、以及整數型的除頻器，簡介完這些架構之後，還有我們這次運用到的跳頻鎖定技術的概念以及電路設計實現的部份，第三部份就是討論模擬結果和部分量測結果的比較，及未來挑戰與設計上加強注意及改進的地方。

The settling time for traditional fast-hopping frequency synthesizer is about several microseconds. It can’t conform to the UWB requirement. There are two types of frequency synthesizers for the UWB system at present. The first type is to use many PLLs and dividers to produce the center of frequency the band needed; the other is to use two or less PLLs with dividers, mixers and multiplexers to obtain all the center frequency of the bands. However, the method is not only complicated but also wastes plenty of area and power. In this study, therefore, we try to use a design scheme to simplify the circuit and realize a fast-switching frequency synthesizer. If the measurement results indicate this scheme practicable, it is expected to utilize such a scheme for the UWB system. We have proposed a method of jumping lock that could barely waste time between switching different bands by controlling the switching signal of VCO and divider appropriately.
In the thesis, there is a method of jumping lock which enables the switching and locking time less than 10ns to fit for the UWB system. We design a PLL for UWB Mode-1 band by utilizing this technology. The VCO achieves the frequency switching among 3.432, 3.96 and 4.488GHz, and the phase noise are -120.1,-119.4 and -120.7dBc/Hz respectively. The charge pump current is about 150 with a variation of +-5%, and an acceptable Vctrl is designed between 0.5-1.3V. The simulation of PLL shows the locking time is less than 10ns which fits for the application of UWB system.
The thesis can be divided into three parts. The first part is to introduce UWB technology background and application as well as our motivation. The second part is probed into the basics of PLL structure, including PFD, CP, LPF, VCO, prescaler and an integer type of frequency counter. After introducing the structure, the concepts of jumping lock technology and circuit design are shown. The third part is to discuss the difference between our simulation and measurement results, in the future. The challenges what we should pay attention to and improve in the future work is also been described.

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