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研究生： 蔡昀霖
Tsai, Yun-Lin
論文名稱： 低計算與低記憶體頻寬之H.264/AVC整數像素點動作估計架構
A Low Computation and Low Memory Bandwidth Architecture for H.264/AVC Integer Motion Estimation
指導教授： 陳中和
Chen, Chung-Ho
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電腦與通信工程研究所
Institute of Computer & Communication Engineering
論文出版年： 2009
畢業學年度： 97
語文別： 中文
論文頁數： 73
中文關鍵詞： 快速搜尋演算法 、視訊編碼 、整數像素點動作估計 、資料共用
外文關鍵詞： Fast search algorithm, Data reuse, Video coding, Integer motion estimation
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    • H.264/AVC視訊壓縮標準採納許多新的視訊壓縮技術來增進壓縮效率與影像畫質，如可變動區塊大小動作估計、多重參考畫面、運動向量預測等。然而這些新的技術也導致視訊編碼的計算複雜度與記憶體存取大幅增加，尤其是整數像素動作估計的部份，佔整個編碼過程74.29%的計算量與77.49%的記憶體存取。因此，快速且有效率的整數像素動作估計之硬體架構設計在即時及低電力消耗應用是不可或缺的。
    本篇論文提出了一個適用於H.264/AVC視訊編碼的整數像素動作估計硬體架構，這個架構是基於一種適用於硬體設計的快速搜尋演算法。我們也提出了有效率的intra-/inter-candidate資料共用策略，以避免不必要的資料計算與記憶體存取。與先前的full search整數像素點動作估計架構相比，我們提出的架構節省了96.7%的資料計算與74.1%的記憶體頻寬，且沒有造成顯著的影像畫質下降。

    H.264/AVC standard adopts many new features such as variable block size motion estimation (VBSME), multiple reference frames, motion vector prediction (MVP), etc, to increase coding efficiency and video quality. However, these features result in extremely high computation complexity and memory accesses in video encoding, especially the integer motion estimation (IME) which requires 74.29% computation and 77.49% memory access requirement of the whole encoder. Thus, a fast and efficient IME architecture is required for real-time and low power application.
    This thesis presents an IME architecture design for H.264/AVC encoder. This architecture is based on a hardware-oriented fast search algorithm. We also propose intra-/inter-candidate data reuse strategies to avoid unnecessary computation and memory accesses. Comparing with previous full search IME architectures, about 96.7% computation and 74.1% memory bandwidth are saved without compromising video quality.

    摘要 I Abstract II 誌謝 III 目錄 IV 表目錄 VII 圖目錄 VIII 第1章 序論 1 1.1 研究動機 1 1.2 研究貢獻 2 1.3 論文編排 2 第2章 背景知識與相關研究 3 2.1 Basic concept of video coding 3 2.2 Overview of H.264 standard 4 2.3 Inter prediction in H.264/AVC encoder 6 2.3.1 Variable block-size motion estimation 7 2.3.2 Motion vector prediction 8 2.4 Concept of electronic system level 10 2.5 Related work 11 2.5.1 Full search IME architecture 11 2.5.2 Fast search algorithm IME architecture 13 第3章 IME演算法及架構設計 15 3.1 Hardware oriented search algorithm 15 3.1.1 Data computing capacity 16 3.1.2 Tri-point search algorithm 17 3.2 Data reuse 19 3.2.1 Inter-candidate data reuse 20 3.2.2 Intra-candidate data reuse 21 第4章 架構實現 26 4.1 Overview 26 4.2 Parallel processing architecture 28 4.3 Memory system 28 4.3.1 Reference window 29 4.3.2 Current macroblock 31 4.3.3 Internal bus 32 4.4 Tri-point processing unit 32 4.5 Data reuse adder tree 36 4.5.2 SAD data register array 37 4.5.3 8×8 block sub-adder tree 39 4.5.4 16×16 block sub-adder tree 41 4.5.5 Data reuse info registers 42 4.6 Search controller 44 4.6.1 Processing unit controller 45 4.6.2 16×16 block controller 48 4.6.3 Dispatch controller 51 第5章 實驗環境與實驗結果 52 5.1 Software/Hardware co-simulation 52 5.2 ESL simulation 53 5.2.2 ESL virtual platform 54 5.2.3 Input of ESL hardware system 55 5.2.4 Modeling of IME modules 56 5.2.5 Parameters setting 58 5.3 Experimental results 60 5.3.1 Different policies of our archtiectures 60 5.3.2 PU number 62 5.3.3 Bus arbitrations 65 5.3.4 Comparison among our work and previous methods 65 5.3.5 PSNR-bitrate curve 68 5.3.6 Simulation time 69 第6章 結論與未來展望 70 6.1 結論 70 6.2 未來展望 70 參考文獻 71

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