| 研究生: |
吳志銘 Wu, Chih-Ming |
|---|---|
| 論文名稱: |
應用場規劃邏輯陣列設計之動態電壓恢復器之研製 A FPGA-Based Design of Dynamic Voltage Restorer |
| 指導教授: |
黃世杰
Huang, Shyh-Jier |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2002 |
| 畢業學年度: | 90 |
| 語文別: | 中文 |
| 論文頁數: | 105 |
| 中文關鍵詞: | 場規劃邏輯陣列 、電壓凹陷 、電壓驟降 、動態電壓恢復器 |
| 外文關鍵詞: | sag, notch, FPGA, DVR |
| 相關次數: | 點閱:89 下載:0 |
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本文提出一新型動態電壓恢復器,並予以應用於保護重要負載,以防止受到市電電壓干擾。傳統動態電壓恢復器對於電壓驟降具良好之補償效果,惟其響應速度過慢,因此無法有效解決如電壓凹陷等電壓暫態問題。對此,本文提出一新型架構,其有別於傳統動態電壓恢復器之輸出濾波器擺設方式,可快速地補償電壓以解決電壓暫態問題。本文控制器係採用類比與數位混合模式,利用場規劃邏輯陣列(Field Programmable Gate Array, FPGA)設計數位控制器,並藉由程式撰寫方式設計電路,以達到快速修改電路參數之優點。本文中實驗波形量測結果,並得知所提之架構確已具供電品質改善之效果,進而證實其可行性及實用價值。
In this paper, the novel deign of dynamic voltage restorer is proposed to protect important loads and restrict the unwanted disturbances. With this proposed circuit design, the drawbacks of traditional dynamic restorers such as slow response and poor voltage transients can be both effectively solved. By allocating the output filters in the appropriate places in the circuit, it is found not only the voltage sag problem can be compensated, but also the voltage transients can be resolved in an efficient manner. To facilitate the circuit design, the field programmable gate array (FPGA) is also employed for the digital controller design in the dynamic voltage restorer, thereby increasing the flexibility of circuit design while improving the dynamic performance significantly. This proposed circuit has been simulated in the laboratory, and experimented through the hardware validation. Test results confirm the feasibility of the deign approach for the applications considered.
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校內:2101-06-26公開