基於由上而下之設計方法以及演算法與架構的共同探索，一個在可重組視訊解碼器裡可支援多個MPEG標準的可重組高產出可變長度解碼器被提出來。目前的工作使用了資料流模型作為演算法及架構的橋樑對不同的標準作探索。為了減少硬體的成本並且增加使用的靈活度，在這些視訊標準裡的共同性藉由在不同的資料處理粒度下分析熵解碼器的解碼流程以及處理單元的架構被萃取出來進而發展出了一個可重組式的架構，藉由可重複使用(reusable)的功能單元(function unit)支援可變長度解碼器(Variable Length Decoder)與內文適應性可變長度解碼器(Context Adaptive Variable Length Decoder)。受惠於在演算法與架構共同設計裡由上而下之設計方法以及在VLD與CAVLD可變長度編碼表共同性的萃取，被提出來的可重組可變長度解碼器可以減少37.5%的記憶體使用量以及46.7%的記憶體面積。另一方面，基於在CAVLD裡的符號LEVEL以及RunBefore有較高的連續發生的機率，多符號解碼器也應用在可重組可變長度解碼器來達到高產出率的效果。此架構使用Verilog HDL實現並且透過TSMC 0.18微米製程技術合成，工作頻率為108MHz，合成面積大約為18.7K閘。所呈現的可重組高產出可變長度解碼器的產出率以及硬體成本超越了目前文獻所記載的科技水平，我們提出的可重組高產出可變長度解碼器可藉由以定義的功能單元來重組並支援在MPEG-2 MP@High的可變長度解碼器以及在AVC/H.264 HP@level 4.2的內文適應性可變長度解碼器。

The thesis presents a high-throughput reconfigurable variable length decoder in Reconfigurable Video Coding (RVC) decoder that is capable for supporting multiple MPEG standards based on the top-down design methodology and algo-rithm/architecture co-exploration (AAC). Current works utilizes dataflow models to bridge algorithm and architecture for possible exploration of various supported stand-ards. To reduce hardware cost and increase flexibility, commonalities amongst multiple standards are extracted at distinct data granularities by analyzing decoding flows and architectures of processing units through the entropy decoder. Hence, develop a reconfigurable architecture which is capable for supporting Variable Length Decoder (VLD) and Context Adaptive Variable Length Decoder (CAVLD) by the definition of reusable function units (FUs). Benefiting from the top-down design in AAC and the commonality extraction on the variable length code tables in VLD and CAVLD, the reconfigurable variable length decoder achieves 37.5% memory usage and 46.7% memory area reduction. In addition, based on the higher consecutive occurrence probability of symbol LEVEL and RunBefore in CAVLD, the multi-symbol decoder for LEVEL and RunBefore is also used in reconfigurable variable length decoder to achieve high throughput-rate. The proposed design is implemented using Verilog HDL and synthesized on 0.18um CMOS technology provided by TSMC. The gate count is about 18.7K gates at a clock constraint of 108MHz. The hardware cost and the throughput of the presented high-throughput reconfigurable variable length decoder has been shown to surpass state-of-arts in the literature and our proposed high-throughput variable length decoder can support VLD in MPEG-2 MP@High level and CAVLD in AVC/H.264 HP@level 4.2 via reconfiguring defined FUs.

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