高位元速度的資料傳送應用如DVD 播放器和Gigabit 以太網路
不斷地需求更高速的類比/數位轉換器。在高速操作下，時脈誤差和
失真現象會限制轉換器的效能。為了達到高速操作而不至惡化失真問
題，一般會比較傾向於使用開回路平行式架構的類比/數位轉換器。
其中，採用折疊與內插式架構的類比/數位轉換器可放鬆其在速度、
準確度與功率消耗上的取捨。
本篇論文即詳細討論一個高速、中等解析度之折疊與內插式類比
/數位轉換器的設計，其涵蓋了三種主要功能，分別是放大、類比前
端處理與比較。為了降低折疊信號達到穩態值所需的時間，因此加入
了短路用開關及一些電路技巧。為了降低偏移誤差進而提高比較的準
確度，本論文提出兩種改良式的平均化技術，經由詳細的分析後可證
明這些技術比之前的方法更能有效地降低偏移誤差。佈局後的模擬結
果證實此類比/數位轉換器可操作在400MS/s ，以及在2.5 伏特的電壓
供應下消耗405mW 的功率。當輸入信號為50MHz 時，可以達到6.1
位元的有效解析度。整個類比/數位轉換器的晶片面積為
1.3x1.6mm
2 ，採用TSMC 0.25um ，1P5M 的CMOS 混和信號製程。

The high-bit-rate data communications such as DVD playback and Gigabit Eth-
ernet are spurring on the conversion rate of A/D converters. With the increasing
conversion rate, the main problems that impair the performance are the timing in-
accuracies and distortions. To provide a fastest path to quantize an analog signal
without aggravating the distortion problems, the parallel A/D architectures by using
only open-loop analog signal processing are preferred. Among them, the folding and
interpolating A/D converter can relax the trade-offs among the speed, accuracy, and
power dissipation.
This thesis examines the design of high-speed, medium-resolution(8 bits) folding
and interpolating A/D converters in terms of three basic functions, namely, amplifica-
tion, analog preprocessing, and comparison. To reduce the settling time for processing
the folded analog signal, shorting switches and some circuit techniques are added. To
perform a precise comparison with less offset, two proposed averaging techniques are
analyzed and proven to be more efficient than the previous implementation. The
post-layout simulation demonstrates the experimental 8-bit A/D converter can clock
at 400MSample/s with a power dissipation of 405mW from a 2.5 V supply voltage.
With a input frequency of 50MHz, 6.1 effective bits are obtained. The chip area is
1.3x1.6mm2 in TSMC 0.25um CMOS 1P5M mixed-signal process.

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