本論文主要探討一個可操作在500MHz十位元的電流導向式數位類比轉換器的設計、分析與實現。此設計使用台積電 0.18 微米製程實現。晶片實際量測結果顯示，差分非線性誤差和積分非線性誤差，分別小於0.35和0.6最小位元。在500MHz的取樣頻率和訊號頻率為25MHz下，SFDR為60.63dB，功率消耗為28mW，核心電路的面積為0.4536 mm2。
此外，本論文也針對電流導向式數位類比轉換器的線性度測試，提出一個電流式內建自我測試的方法。此架構主要由電流相減電路和電流控制震盪器所組成。藉由量測電流差和搭配selected-code 測試方法，將可大大降低數位類比轉換器所需耗費的測試時間，並且減少高精確度量測儀器的需求，故可以減少相當可觀的測試成本。

This thesis presents the design concept, circuit analysis, and practical considerations of implementation for a 10-bit 500-MSample/s current steering digital-to-analog converter. It is fabricated in TSMC standard 0.18-m 1P6M CMOS process. The measured results show that the differential nonlinearity (DNL) is less than 0.35 LSB (Least Significant Bit), and the integral nonlinearity (INL) is less than 0.6 LSB. The spurious free dynamic range (SFDR) is 60.63 dB with a 25-MHz input signal at a 500-MS/s sampling rate. The power consumption is 28 mW, and the core area is 0.4536 mm2.
Moreover, a current-mode Built-In Self-Test (BIST) scheme is proposed for on-chip estimating static non-linearity errors in current-steering digital-to-analog converters. This scheme includes the current subtraction circuit to increase the sampling current accuracy and the selected-code method to reduce the testing time. As a result, the proposed method can greatly shorten the test time and relax the demands on high precision test equipments, and consequently reduce test cost significantly.

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