在非二位元低密度同位元檢查(Non-Binary Low-Density Parity-Check, NB-LDPC)碼解碼器的架構設計上，運算複雜度相當的高，需要的記憶體用量也相當龐大。因此，如何降低運算複雜度與記憶體用量，也成了目前設計上最重要的一環。
為了降低實作上符元搜索的複雜度，現今的解碼器設計大多使用前向後向解碼方式(Forward-Backward Decoding Scheme)，但是使用此方法，需要大量額外的記憶體面積來儲存暫時資料，而且完成前向、後向、合併三次運算的過程中，也增加了運算時間。為了降低記憶體使用量與計算複雜度，本論文中提出了僅需前向運算的解碼方式，並且藉由最小最大解碼演算法(Min-Max Decoding Algorithm)的特性，回推出適當的解碼結果。另外，為了提升整體解碼速度，此改良式解碼器可降低運算所需次數，並且藉由平行處理的方式來提升整體的運算速度。最後由分析結果可知，所提出之解碼架構可有效的降低整體記憶體的使用量與計算複雜度。

Non-binary low-density parity-check (NB-LDPC) codes have better error correcting ability than binary LDPC codes when the code length is moderate. However, the hardware cost of the NB-LDPC decoder is much larger than that of the binary one. According to the related NB-LDPC decoder designs, memory usually occupies a substantial portion of the total chip area, and the corresponding computational complexity is rather high. Therefore, the most important topic in NB-LDPC decoder design is to find an efficient way to reduce the computational complexity and the memory usage amount.
In related works, The CNU commonly applied the forward-backward decoding scheme to reduce the symbol searching complexity, but it requires extra memory area for storing intermediate messages. Additionally, this method increases the decoding latency due to the long computation time of forward, backward and merging steps. To reduce the computational complexity and memory usage amount, we proposed the max-forward decoding scheme, which only needs to compute the forward steps and calculate the messages by using the properties of min-max decoding algorithm to backtrack the proper value from maximum and second maximum value. The thesis also presented a modified min-max decoder to eliminate the redundant computation and increase the decoding speed by using the concept of parallel processing. Finally, the proposed decoding architecture can reduce the memory usage amount and the computational complexity from our analysis results.

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