本論文提出兩種新穎的電路架構以實現高速度及低功率之全平行內容可定址記憶體設計。這兩種電路架構分別為：1. 以預先計算為基礎之內容可定址記憶體設計及 2. 虛擬-互補式金氧半內容可定址記憶體設計。基於靜態的電路設計，這兩種電路架構不僅可以提升電路效能，也可以克服傳統動態電路中的各種設計問題。為了降低靜態功率及大部分的比較功率消耗，本篇論文提出數種電路設計方法以達到高速度及低功率消耗的內容可定址記憶體設計。
　　在提出的以預先計算為基礎之內容可定址記憶體設計中，基於預先計算機制，不但可以降低內容可定址記憶體整體的功率消耗，更可以減少內容可定址記憶體細胞所需的電晶體數。整體電路已在 TSMC 0.35 μm 金氧半製程下製作並完成驗證。以一個內容大小為 128 × 30 之內容可定址記憶體，經由實際量測結果得知本論文所提出的電路架構在 3.3 V 的電壓供應下，資料搜尋速度達每秒 100 百萬筆，且功率消耗低於 33 mW。因此，本電路適合使用在OC-768 非同步傳輸模式交換機網路中。
　　在提出的虛擬-互補式金氧半內容可定址記憶體設計中，基於虛擬-互補式金氧半邏輯設計，不但可以有效提升內容可定址記憶體字組的資料比較速度，而且減少內容可定址記憶體的功率消耗。除傳統的二元內容可定址記憶體，本篇論文提出一種新的四元內容可定址記憶體以提供不同的資料搜尋功能。整體電路已在 TSMC 0.35 μm 金氧半製程下製作並完成驗證。在二元內容可定址記憶體設計方面，以一個內容大小為 128 × 30 之內容可定址記憶體，經由實際量測結果得知本論文所提出的電路架構在 3.3 V的電壓供應下，資料搜尋速度達每秒 110 百萬筆，且功率消耗低於 23 mW。除此之外，由量測中亦可發現本電路在低達 1.5 V 的供應電壓下，資料搜尋速度達每秒 32 百萬筆。在四元內容可定址記憶體設計方面，以一個內容大小為 128 × 30 之內容可定址記憶體，經由實際量測結果得知本論文所提出的電路架構在 3.3 V的電壓供應下，資料搜尋速度達每秒 94 百萬筆，且功率消耗低於 29 mW。除此之外，由量測中亦可發現本電路在低達 1.4 V 的供應電壓下，資料搜尋速度達每秒 15 百萬筆。因此，本電路亦適合使用在OC-768 非同步傳輸模式交換機網路中。
　　基於所提出的虛擬-互補式金氧半二元內容可定址記憶體設計，本篇論文提出一個高速度及低功率消耗的最長資料比對電路設計。以一個內容大小為 128 × 32 之記憶體容量，經模擬評估結果得知此電路在 3.3 V的電壓供應下，資料搜尋速度達每秒 66 百萬筆，且功率消耗低於 150 mW。因此，本篇論文所提出的最長資料比對電路符合現今高速網路對資料比對速度的需求，例如十億位元乙太網路中。

　　This thesis presents two novel VLSI architectures for high-speed and low-power fully parallel CAM design. These two proposed architectures are 1) precomputation-based content-addressable memory (PB-CAM) and 2) pseudo-CMOS content-addressable memory (PC-CAM). The proposed PB-CAM and PC-CAM architectures adopt static pseudo-nMOS circuit design that not only improves circuit performance but also solves some design problems of dynamic CMOS circuit design. To reduce the static power and majority part of comparison power dissipations of pseudo-nMOS circuit design, some low power design techniques are used in the proposed PB-CAM and PC-CAM architectures to achieve high-speed and low-power features.
　　In the proposed PB-CAM architecture, this design is based on a precomputation approach that saves not only power consumption of the CAM system, but also reduces transistor count and operating voltage of the CAM cell. The whole design was fabricated with the TSMC 0.35 μm SPQM CMOS process. With a 128 words by 30 bits CAM size, the measurement results indicate that the proposed circuit works up to 100 MHz with the power consumption of 33 mW at 3.3 V supply voltage and works up to 30 MHz under 1.5 V supply voltage. The PB-CAM circuit is suitable for OC-768 ATM switch.
　　In the proposed PC-CAM architecture, this design is based on a proposed static pseudo-CMOS logic structure that not only improves comparison speed of the PC-CAM word circuit, but also reduces power dissipation of the PC-CAM system. In addition to the conventional binary CAM (BCAM) circuit design, a new quadruple CAM (QCAM) circuit design is proposed to achieve alternative search function. The proposed PC-BCAM and PC-QCAM were fabricated with the TSMC 0.35 μm single-poly quadruple-metal (SPQM) CMOS process. With a 128 words by 30 bits CAM size, the measurement results indicate that the proposed PC-BCAM and PC-QCAM circuits work up to 110 Msearches/sec and 94 Msearches/sec with the power consumption of 23 mW and 29 mW, respectively. Therefore, The PC-BCAM and PC-QCAM circuits are suitable for OC-768 ATM switch.
　　Based on the proposed PC-BCAM architecture, a high-speed, low-power, and low-cost LPM search engine was proposed in the thesis. With a 128 prefix data by 32 bits size, the estimation results show that the searching speed of the circuit achieves up to 66 MHz with power consumption less than 150 mW at 3.3 V. The estimated results show that the proposed LPM search engine meets multi-gigabit/s high-speed networking requirement, for example gigabit Ethernet.

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