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研究生: 王振華
Wang, Chen-Hua
論文名稱: 應用於網路卸載引擎之iWARP協定組的設計與實作
Design and Implementation of iWARP Protocol Suite for a Network Offload Engine
指導教授: 陳中和
Chen, Chung-Ho
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電腦與通信工程研究所
Institute of Computer & Communication Engineering
論文出版年: 2007
畢業學年度: 95
語文別: 英文
論文頁數: 99
中文關鍵詞: 遠端DMA存取iWARP協定組TCP/IP協定TCP/IP卸載引擎直接資料搬移
外文關鍵詞: TCP/IP offload engine, TCP/IP stack, RDMA, DDP, iWARP protocol suite
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  • 傳統的TCP/IP協定架構中,TCP提供可靠性的服務給上層,因此接收端的TCP保證送交上層的資料具有完整性及正確的順序。為了達到此目的,TCP收到的封包必須先經過暫存甚至重組的步驟,才能放進應用程式的記憶體空間裡。在高速的網路環境下,TCP內部的重組及複製資料的動作會浪費記憶體匯流排的頻寬、增加CPU處理資料的時間、需要額外的記憶體空間來放置資料,以及浪費多餘的時間在資料的搬移上,因而使得網路處理的效能大受影響。新訂定的iWARP協定組的主要功能便是支援遠端DMA存取(Remote DMA, RDMA)以及直接資料搬移(Direct Data Placement, DDP),可以把收到的資料直接放到最終將被使用的記憶體空間中,並利用此空間進行資料重組,以取代原本TCP內部所需的重組緩衝區,進而消除不必要的資料搬移。

    本篇論文中提出一個實現iWARP協定組的架構,並探討此架構與現有TCP/IP卸載引擎(TCP/IP Offload Engine, TOE)的整合方式。此設計以實現標頭處理的硬體為主,可支援8條連線同時運作。使用UMC 0.18 的技術,目前處理速度可達到1-Gbps的乙太網路需求,並使用了139K個邏輯閘。此外,我們模擬出一個TOE的環境,實驗結果說明若是接收到的封包有亂序的情形發生時,整合了iWARP協定組的TOE可以大大減少網路卡上記憶體的使用量以及每個封包的平均等待時間。

    In the architecture of traditional TCP/IP stack, TCP provides the upper layer with reliability. TCP at the receiving side must ensure the integrity and in-order of the data before it can be delivered to the host. Thus received TCP packets must be temporarily stored and even reassembled before they are submitted to the application’s memory space. In the environment of high-speed network, reassembly and data copy involve high demands on memory bus bandwidth, increases on the CPU processing overhead, extra memory space to store packets, and redundant time to move the data. The performance of network processing is therefore getting worse. The main features of the newly-proposed iWARP protocol suite are supporting remote DMA (RDMA) and direct data placement (DDP). Thus the received data can be directly placed into the destination memory space of application where they can be reassembled as well, so that the reassembly buffer required in TCP layer and unnecessary data copies can be removed.

    We propose an architecture to implement the iWARP protocol suite in this thesis, and describe how we can integrate the design with the existing TCP/IP offload engine (TOE). Our design is a state machine based hardware that focuses on the header processing, and currently supports up to 8 connections at the same time. Using the technology of UMC 0.18, our design can meet the wire speed of 1-Gbps Ethernet, requiring about 139K gate count. In addition, we simulate a TOE environment, and the results of experiments show that the TOE integrated with our iWARP design can drastically reduce the memory requirement and average queuing time per packet on the network interface card (NIC).

    LIST OF TABLES IV LIST OF FIGURES V CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 CONTRIBUTIONS OF THE THESIS 3 1.3 OVERVIEW OF THE THESIS 4 CHAPTER 2 RELATED WORK 5 2.1 HARDWARE AND SOFTWARE IMPLEMENTATION 5 2.1.1 NE010 iWARP Ethernet channel adapter 5 2.1.2 Compatibility of iWARP for regular network adapters 6 2.1.3 Implementation of iWARP in software 6 2.2 ANALYSIS OF OPEN SOURCE CODE 8 2.2.1 Analysis of test programs 9 2.2.2 Analysis of connection establishment 10 2.2.3 Analysis of transferring a Send-type message 11 2.2.4 Analysis of transferring an RDMA Read Request 12 2.2.5 Analysis of transferring an RDMA Write message 12 CHAPTER 3 ARCHITECTURE 13 3.1 DESIGN SPECIFICATION 13 3.1.1 Alternatives for the implementation 13 3.2 DESIGN CONCEPTS 15 3.2.1 Data flow of protocol payload and header 15 3.2.2 Logical view of the design 17 3.3 OVERALL ARCHITECTURE 19 3.3.1 System architecture 19 3.3.2 Buffer management 20 3.3.3 Data pointer format 22 3.3.4 MTB and inter-module communication 23 3.3.5 Connection table architecture 27 3.3.6 Framework of protocol modules 28 3.4 PROTOCOL MODULES 30 3.4.1 MPA layer 30 3.4.1.1 Parallel 32-bit CRC module 31 3.4.1.2 MPA connection table 34 3.4.1.3 MPA_Tx module 35 3.4.1.4 MPA_Rx module 36 3.4.2 DDP layer 37 3.4.2.1 MSN table 37 3.4.2.2 Reassembly table 38 3.4.2.3 DDP_Tx module 40 3.4.2.4 DDP_Rx module 42 3.4.3 RDMA layer 44 3.4.3.1 Register_Handler_Tx module 44 3.4.3.2 Register_Handler_Rx module 46 3.4.3.3 STag table 47 3.4.3.4 RDMA_Tx module 48 3.4.3.5 RDMA_Rx module 49 3.5 USER INTERFACE REGISTERS 50 3.5.1 Command status register 51 3.5.2 PDU information register 51 3.5.3 Connection establishment registers 52 3.5.4 Interrupt register and status reply registers 53 3.5.5 Usage of registers 53 3.6 DATA FLOW 55 CHAPTER 4 VERIFICATION AND PERFORMANCE ESTIMATION 58 4.1 VERIFICATION METHODOLOGY 58 4.2 SYNTHESIS RESULTS 59 4.3 PERFORMANCE ESTIMATION 60 4.4 PROTOTYPING VERIFICATION 64 CHAPTER 5 SIMULATION SYSTEM AND RESULTS 66 5.1 SYSTEM MODEL 66 5.1.1 Generic TOE vs. MPA-aware TOE 66 5.1.2 Simulation system 67 5.2 RESULTS AND ANALYSIS 70 5.2.1 Queuing time 71 5.2.2 Memory requirement 72 5.2.3 Throughput 75 CHAPTER 6 CONCLUSIONS 78 REFERENCES 79 APPENDIX A IWARP SPECIFICATION 81 A.1 IWARP LAYERING 81 A.1.1 Marker-based PDU Aligned Framing for TCP (MPA) 81 A.1.1.1 Overview 81 A.1.1.2 Header format 82 A.1.2 Direct Data Placement (DDP) 84 A.1.2.1 Overview 84 A.1.2.2 Header format 84 A.1.2.3 Data transfer considerations 87 A.1.3 Remote Direct Memory Access (RDMA) 90 A.1.3.1 Overview 90 A.1.3.2 Header format 92 A.2 IWARP MESSAGE FORMATS 95 APPENDIX B VITA 99

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