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研究生：	蕭景瑞 Hsiao, Ching-Jui
論文名稱：	應用於多標準可重組視訊解碼器之微程式控制可重組語法分析器 Reconfigurable Parser for Multi-standard Reconfigurable Video Coding Decoder with Microprogrammed Control
指導教授：	李國君 Lee, Gwo-Giun
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2011
畢業學年度：	99
語文別：	英文
論文頁數：	77
中文關鍵詞：	語法分析器、可重組架構、微程式控制
外文關鍵詞：	Parser, Reconfigurable Architecture, Microprogrammed Control
相關次數：	點閱：111 下載：3
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本論文中，利用微程式控制可抽換微碼的高彈性度，我們提出具高彈性可應用於多標準可重組視訊解碼器的可重組語法分析器。基於由上而下的設計方式，由於語法分析器的回饋式控制，加入微程式控制的考量去精煉高層級資料流至低層級以得到我們所提出操作於108MHz下的可重組語法分析器之架構，藉由萃取控制上的共通性以得到部分共用的微指令格式，能夠省去可重組資料路徑上切換不同標準之控制。由於1920x1088@60fps的高規格應用有高輸出率的要求，定義有效率的微指令也因此受限，在此限制條件下，我們提出的微指令集不僅能提升彈性度，與分開獨立實現並以TSMC 0.18微米製程合成的有限狀態機控制相較下，在輸出控制邏輯部分更省去20.29%的邏輯閘數，由於微指令格式的高比例共用，當加入新的標準時，我們可以想像到更高百分比的節省。透過此可重組控制單元的個案研究，我們可以說針對可重組視訊編碼或其他多用途之應用，微程式控制將成為趨勢。

In this thesis, utilizing the characteristic of high flexibility in microprogrammed control with reloadable microcode, a highly flexible reconfigurable parser for multi-standard reconfigurable video coding decoder is proposed. Based on top-down design methodology, the high level dataflow is refined into low level, with microprogrammed control taken into consideration due to the nature of feedback control in parser, to achieve the proposed architecture of reconfigurable parser which operates at 108MHz . The commonalities in control are extracted to form the partially shared format of microinstruction which also saves the switching control between standards for reconfigurable datapath. Due to high throughput demand in high-end application, i.e. 1920x1088@60fps, defining effective microinstruction is quite limited. Under such limitation, the proposed microinstruction set for microprogrammed control not only raises the flexibility but also saves 20.29% gate count as compared to individually implemented finite state machine based control in output control logic synthesized in TSMC 0.18 μm technology. Owing to the high proportion of shared format of microinstruction, the higher saving percentage can be envisioned when one another video coding standard is involved in the reconfigurable parser. As a case study of reconfigurable control unit, we claim that microprogrammed control is the trend for reconfigurable video coding or other multi-purpose application.

Chapter 1	Introduction	1
1	Video Coding	1
1.1	Reconfigurable Video Coding	2
2	Motivation	2
3	Organization of This Thesis	3
Chapter 2	Overview of MPEG-2 and AVC/H.264 Standard	4
1	Introduction to MPEG-2 Standard	4
2	Introduction to AVC/H.264 Standard	6
2.1	Entropy Coding	7
2.2	Inverse Quantization	7
2.3	Inverse Transform	8
2.4	Intra Prediction	8
2.5	Inter Prediction	9
2.6	Deblocking Filter	9
3	Introduction to Parser in MPEG-2 and AVC/H.264	9
Chapter 3	RVC Decoder	12
1	Introduction to Algorithm/Architecture Co-exploration	12
2	Specification	13
3	High Level Dataflow Model of RVC Decoder	14
3.1	High Level Block Diagram	14
3.2	High Level Dataflow Scheduling	16
3.2.1	Processing Granularity and Processing Order	16
3.2.2	Decoding Schedule	18
3.3	High Level Dataflow Model in System C	19
4	System Architecture	20
4.1	Software/Hardware Partition	20
4.2	Dual-Bus	22
4.3	Memory Controller	22
4.4	System Controller	22
4.5	Control Register and Status Register	23
Chapter 4	Behavior of Reconfigurable Parser	25
1	Parsing Flow	25
2	Parsing Process	28
2.1	Fixed Length Code	31
2.2	Exp-Golomb Code	32
2.3	Not Exist Syntax Elements	33
Chapter 5	Proposed Reconfigurable Parser with Microprogrammed Control	35
1	Flexibility in Reconfigurable Architecture	35
2	Low Level Dataflow of Reconfigurable Parser	37
2.1	Block Diagram and Scheduling Table	37
2.1.1	Without Control	37
2.1.2	With Microprogrammed Control	38
2.1.3	Final Adoption	40
3	Control Flow	45
4	Pre-process Scheme for Real-time Constraint	48
5	Commonality Extraction for Reconfigurable Parser	50
5.1	Reconfigurable Exp-Golomb Code Parser	52
5.2	Shared Syntax Element Registers	53
5.3	Entropy-SysCtrl FIFO	54
5.4	Microsequencer	57
6	Design of Microprogrammed Control	61
6.1	Microinstruction	61
6.1.1	Shared Format of Microinstruction	61
6.2	Microcode	65
6.2.1	Vertical Microcode	65
6.2.2	Memory Configuration	67
6.3	Proposed Microarchitecture of Microprogrammed Control	68
7	Proposed Architecture of Reconfigurable Parser	68
Chapter 6	Experimental Result and Verification	70
1	Experimental Result	70
2	Verification	73
Chapter 7	Conclusion and Future Work	74
1	Conclusion	74
2	Future Work	75
Reference	76

                                    

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校內：2021-12-31公開
校外：2021-12-31公開

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