多媒體音訊應用上大多需要大量高維度的運算，隨著智慧生活範疇的延伸，最常使用於自然人機介面中的語者語音辨識(Speaker-Speech Recognition)應用已漸漸被重視，語者語音辨識應用上需要多種功能如擷取、訓練與辨識等，而現今晶片架構大多為單一元件設計，且為高單價較無針對語者語音辨識應用而設計具整體性的架構。可重組運算(Reconfigurable Computing)一直以來大多應用在低成本需求的FPGA，而多核心架構(Multi-Core Architecture)也是常用於處理高維度運算之晶片架構。基於可重組式多核心架構結合，本論文提出一新穎多核心架構，具多自我重組模態(Self-reconfigurable mode)與預先重組模態(Pre-configurable mode)之結合以兼顧低成本與高效能之功效，主要在於針對語者語音辨識上需求功能包含擷取辨識與訓練(ERL: Extraction, Recognition, and Learning)，而設計具低成本且具能及時處理高維度運算之晶片架構設計。
在第一部份，首先，我們利用軟硬體協同設計來初步分析此系統的運算瓶頸與加速需求，接著第二部份，針對訓練階段(Learning Phase)下的運算瓶頸即訓練(Learning)部分實現硬體加速設計，實現方法以可重組架構設計出三種可使用的模態(Tri-mode Reconfigurable)，此架構較先前期刊有較好的硬體使用效率，因此可在低成本條件下，兼具有高速運算的能力，並且在0.18微米製程下，進行初步的晶片效能模擬，此晶片的面積為8.6 mm2，功耗為77.33 mW，可以達到較先前設計節省31%的邏輯閘數並有16倍的訓練加速。
在第三部份，為考量整體系統效能，將擷取與辨識(Extraction and Recognition)硬體納入設計之考量，由於在辨識階段(Testing Phase)下的擷取會變成運算瓶頸，因此僅針對擷取進行加速，辨識部分則採用低成本之考量，在初步以90奈米製程下進行晶片效能模擬，此晶片的面積為4.3 mm2，功耗為8.9 mW，需增加26%的邏輯閘數(723K gate count)，但可以達到較多的功能運算並有3倍的擷取加速。而後，我們再有效的整合擷取與辨識架構至可重組架構中，讓可重組多核架構具有五種自我重組模態與4種預先重組模態的混合，並減少17%的邏輯閘數(603K gate count)，而仍可以一樣達到較多的功能運算並有3倍的擷取加速。
在第四部份，需求在於更低成本考量，因此我們提出二元對分分群演算法(Binary Halved Clustering)來取代原本的循序最小最佳化(Sequential Minimal Optimization)訓練方法，此演算法相較於常用的分群演算法K-means依然可節省87%運算量，並且平均辨識率仍可達到92.7%，使此系統應用在語者語音辨識(ASSR: Automatic Speaker-Speech Recognition)的此案例中，同時具有低運算時間及高辨識的功效，在以90奈米製程下進行晶片效能模擬，此晶片的面積為2.2 mm2 (395 K gate count)，功耗為8.74 mW。

In multimedia applications, audio processing usually requires amounts of high-dimensional computations. When intelligent applications grow up, automatic speaker-speech recognition (ASSR), which requires extraction, recognition, and learning (ERL) functions, are more and more popular. Conventional VLSI designs focus on the enhancement of single component; in addition, most chip solutions belong to high-cost and non-specified design for ASSR. This dissertation proposes a novel reconfigurable multi-core architecture which has five self-reconfigurable modes and four pre-configurable modes for low cost and high efficiency. According to this architecture, this work focuses on ASSR to design a high-dimensional processing ability chip with real-time performance.
In the first part of this dissertation, this work uses a hardware/software co-design to analyze the bottleneck of whole ERL system. In the second part of this dissertation, in the bottleneck of training phase, learning is realized by hardware acceleration which has tri-mode reconfigurable ability. Compared with the baseline, the proposed work has higher usage rate of hardware. Therefore, in a low-cost limitation, this work still has high speed factor. The work is completed based on a standard library for 0.18 um CMOS technology. The chip requires a die size of 8.6 mm2 and a power comsuption of 77.33 mW to achieve 31% less gate count and 16-fold improvement of learning speed.
In the third part of this dissertation, to consider the performance of whole ERL system, extraction and recognition hardware are integrated into the previous design. Because the bottleneck of testing phase comes to the extraction part, the hardware acceleration of extraction is realized. The hardware of recognition is designed for low cost. The work is manufactured based on a standard library for 90 nm CMOS technology. The chip requires a die size of 4.3 mm2 and a power comsuption of 8.9 mW to achieve 3-fold improvement of extraction speed with 26% increase of gate count. The next work integrates extraction and recognition architecture into reconfigurable architecture efficiently. The reconfigurable architecture becomes the mixing of five self-reconfigurable modes and four pre-configurable modes. The simulation results show that 3-fold improvement of extraction speed requires 17% decrease of gate count.
In the fourth part of this dissertation, the specification is to achieve lower cost. Accordingly, this work presents a novel algorithm, namely binary halved clustering (BHC) to replace the conventional training method, that is, sequential minimal optimization (SMO). Compared with the popular algorithm, K-means, the proposed algorithm can save 87% less computational quantity and an average accuracy of 92.7%. This system can be applied in a case study of automatic speech-speaker recognition, and it achieves both low-computation time and high accuracy. This work is also manufactured based on a standard library for 90 nm CMOS technology. The chip requires a die size of 2.2 mm2 and a power comsuption of 8.74 mW.

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