本論文之研究可分為三大主要部份：第一部份為針對現今毫米波除頻器的發展需求，研究一個雙模態除三及除五直接注入鎖定頻率除頻器。為了達到具雙模除數功能之除頻器，我們先以注入鎖定除三除頻器為基礎，並將LC串聯共振的方法及切換電感之電路技巧應用於該電路架構中，使除頻器可經由一控制信號來進行除頻器共模點阻抗的切換，透過直接注入的混頻機制，電路將可以由控制信號來決定完成40 GHz除五或24 GHz除三的功能，達到雙模態除頻器的實現。此除頻器將有助未來整合一個雙模頻率合成器。此雙模態除頻器在核心電壓1.8 V的操作下，且注入信號大小為+4 dBm時，經由量測得到除三功能在調整電壓為1.8 V下有最大鎖定的範圍由23.8 GHz至27.0 GHz(總共3.2 GHz)，調整電壓由0 V至1.8 V之總操作範圍由22.5 GHz至27.0 GHz(總共4.5 GHz)；除五功能在調整電壓為1.8 V下有最大鎖定的範圍由40.67 GHz至41.55 GH(總共880 MHz)，調整電壓由0 V至1.8 V之總操作範圍由38.23 GHz至41.55 GHz(總共3.32 GHz)。除頻器整體晶片面積為0.65 × 0.75 mm2，不包含輸出緩衝級之下的消耗功率為17.02 mW 。
第二部份為延續第一部份之雙模態除頻器於鎖相迴路設計中。由於除五高除數的功能在高頻鎖相迴路中有著多項優勢，在經由量測驗證上述雙模態除頻器的功能正確後，我們將其除頻器整合並實現一個操作在24 GHz之鎖相迴路。在輸入的參考頻率為400 MHz下，此鎖相迴路可以同時提供ISM 24 GHz、5 GHz、2.4 GHz及900 MHz四個應用頻帶升降頻所需之本地振盪信號，其目的即是將不同頻帶同步降到共同中頻(零中頻或是低中頻)，使其後面整個路徑的方塊電路皆可以直接共用整合，方便未來整合多頻帶射頻收發機，以達到電路共用最大化，朝向高性能、高整合度、低成本和低功率方向發展。由模擬資料顯示此鎖相迴路的壓控振盪器可調頻率由22.78 GHz至25.60 GHz (共2.82 GHz)，其相位雜訊在頻率位移為10 MHz時為-112.03 dBc/Hz，輸出功率為-6 dBm。包含Bonding pads的鎖相迴路整體晶片面積為1.28 × 1.34 mm2，不包含輸出緩衝級之消耗功率為38.11 mW。第一部份的雙模態除頻器與第二部份的鎖相迴路皆利用台積電0.18 m 1P6M CMOS製程完成其晶片設計。
第三部份有別於前兩部份所使用之製程，我們將研究與探討使用3DIC先進製程對於射頻切換電感與振盪器之影響，而其影響主要來自於3DIC製程中用以連接上下晶圓的矽穿孔(Through silicon via, TSV)技術所造成。應用TSV技術雖然可以將二維晶片以低阻值TSV連接轉變成三維的立體堆疊型態，有效的善用空間並縮短傳輸距離，提供多功能整合、高效能、低功耗等許多優點，但考量電路在高速下操作及多層晶片堆疊時，直徑接近30 μm且高度接近70 μm的TSV其寄生電感、電阻效應所造成的影響，也必須在設計射頻與高速混合訊號電路納入考量。我們驗證TSV的方法是先根據工研院電光所提供的相關製程資料建立模擬環境來模擬所需電路，並將TSV以電感等效模型的方式建立其等效模型，再透過模擬及下線來驗証TSV應用於射頻與高速混合訊號電路下的可靠性、可行性與穩定性。同時，我們將對該製程下之TSV的電性做分析研究。預計未來與CAD設計軟體進行整合以提供3DIC設計所使用，將可加速3DIC TSV技術之發展與應用。第三部份關於3DIC先進製程的研究內容附於本論文附錄中。

This thesis aims to the study of RF circuits in CMOS and 3DIC processes. The study is divided into three major parts: the first part is to design a dual-mode divide-by-3/-5 injection locked frequency divider for the present needs of frequency divider development. By utilizing a switchable band pass filter (BPF) in the differential injector, the second- or fourth-harmonic can be peaked at the common-source node of the injector transistors. The input injection signal can mix with the correspondingly peaked harmonic to achieve the division-by-3 or division-by-5 function. With an injection power level of +4 dBm, the locking ranges of 3.2 GHz (for division-by-3) and 880 MHz (for division-by-5) are achieved at Vtune = 1.8 V. The total operation ranges for the division-by-3 and division-by-5 modes are from 22.5 to 27.0 GHz (total 4.5 GHz) and from 38.23 to 41.55 GHz (total 3.32 GHz), respectively, as Vtune increases from 0 to 1.8 V. The divider core consumes 17.02 mW at 1 V supply voltage. The total chip area is 0.65 × 0.75 mm2.
The second part of ths thesis is to implement a phase-locked loop (PLL) which can operate at 24 GHz with 528 MHz reference input and its output frequencies can be suitable for ISM 24 GHz, 5 GHz, 2.4 GHz and 900 MHz band application. By integrating the dual-mode divider developed in the first part, the first stage divider in the prescaler of a PLL with a higher division ratio can reduce the total numbers of following divider stages. Therefore, the power dissipation and area consumption can be greatly saved. The simulation show that the tuning range of the VCO on PLL is from 22.78 GHz to 25.60 GHz (total 2.82 GHz) as Vctrl increases from 0 to 1.8 V. The phase noise is -112.03 dBc/Hz at 10 MHz offset from the center frequency. The output power is -6 dBm. The total chip area is 1.28 × 1.34 mm2 and the power consumption is 38.11 mW, excluding that of output buffers.
Unlike the circuits in the first two parts which were fabricated in a TSMC 0.18 μm 1P6M CMOS process, in the third part of this thesis the effects of 3DIC technology on the circuit performances of RF switchable inductors and oscillators, especially the effects of through silicon via (TSV) on the circuit performances have been investigated. Utilizing the TSV technology will improve the reduce the lengths of signal lines by way of connecting the devices with shorter interconnection lines as compared with those a planar layout with 3D stack structure. By this way, the multi-functional integrations with high performance and low-power consumption can be realized. However, under the considerations of high-speed operation and multi-layer stacking, the parasitic capacitive and inductive parasitic from the TSV with about 70-μm should be taken into account when designing the RF front-ends and high-speed mixed-signal integrated circuits. At present, we finish the testkey design (including ten sets of spiral inductors in traditional and 3D stacked layout topologies, respectively, and two sets of switchable inductors in three-dimensional stacked layout topology, and sex sets of spiral inductor in BEOL process) and the circuit design (including two VCOs in stacked topology and a ring oscillator in three different layout topologies with different amount of TSV). We have finished the simulation and layout works of six testkeys and taped out these testkeys as scheduled. The testkeys are still under fabrication. In the near future, we can figure out the effect of TSV on RF and high-speed mixed-signal integrated circuits. We will also do the analysis of measurement data and build up the related model of inductors to speed up the development of RF integrated circuits in the ITRI EOL’s 3DIC process.

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