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研究生：	邱永明 Chiu, Yung-Ming
論文名稱：	應用於2.4及5.7GHz 802.11 WLAN之CMOS單晶射頻積體電路 Design of 2.4GHz and 5.7GHz CMOS RFICs For IEEE 802.11 WLAN Application
指導教授：	莊惠如 Chuang, Huey-Ru
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2003
畢業學年度：	91
語文別：	中文
論文頁數：	161
中文關鍵詞：	射頻、接收機、雜訊指數、相位雜訊、混波器、頻率合成器
外文關鍵詞：	IC, LNA, mixer, VCO, CMOS, synthesizer, RF, PA, phase noise, noise figure, receiver
相關次數：	點閱：112 下載：7
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本論文係以CMOS製程研製應用於IEEE 802.11 WLAN降頻器之CMOS RFIC。第一部份在ISM頻帶以UMC 0.18mm 1P6M CMOS製程製作，射頻範圍為2.4~2.483 GHz，經2.038~2.098GHz本地振盪器降至固定中頻374MHz。共計電路有鏡像抑制低雜訊放大器、雙端平衡混波器、LC-tank VCO及差動功率放大器。其中差動功率放大器，線性增益為12.6dB，1dB輸出增益壓縮點為19dBm，功率增加效率為14.2%。VCO與Motorola MC12210 PLL晶片組成一頻率合成器，其相位雜訊測得-97.31dBc/Hz @100KHz。將低雜訊放大器、雙端平衡混波器及帶通濾波器組成接收模組，經量測得其雜訊指數約8.94dB、增益約17.23dB、input P1dB約-26.5dBm，鏡像抑制能力約56dB。在數位訊號量測方面，以802.11b DSSS (Modulation: CCK) 且訊號傳送速率為11Mbps時，測得EVM值為5.54%; 當訊號為OFDM (Modulation: 64-QAM)，且傳送速率為54Mbps時，測得EVM為2.2%。
本論文第二部份以TSMC 0.25mm 1P5M CMOS製程製作應用於IEEE 802.11a WLAN U-NII頻帶降頻器之CMOS RFIC。射頻範圍為5.725 ~ 5.825 GHz，經6.225~6.285GHz本地振盪器降至固定中頻480MHz。共計電路有電流共用低雜訊放大器、雙端平衡混波器及一組6GHz混成頻率合成器。在電流共用低雜訊放大器前串接一級discrete低雜訊放大器，並與雙端平衡混波器及帶通濾波器組成接收模組進行整合測試，量測得雜訊指數約6.25dB、增益約16dB、input P1dB約-21dBm，鏡像抑制能力約59.4dB。在數位訊號量測方面，當OFDM訊號傳送速率為54Mbps (Modulation: 64-QAM)時，測得EVM為1.43%。6GHz混成頻率合成器係以Hittite VCO晶片、除頻器及Motorola MC12210 PLL晶片實現，其相位雜訊測得-89.65dBc/Hz @100KHz。

This thesis presents the design and implementation of CMOS RFICs for IEEE 802.11b/g WLAN RF front-end in a UMC 0.18mm CMOS process. The developed 2.4GHz CMOS RFICs includes an image reject LNA, mixer, VCO and differential PA. For a heterodyne CMOS RF receiver, the RF is from 2.4 to 2.483GHz and the IF is at 374 MHz. The CMOS VCO has an output frequency from 1720 to 1914MHz with -97.31dBc / Hz@100kHz phase noise. The VCO with a Motorola MC12210 PLL chip form a frequency synthesizer. The 2.4GHz CMOS RF heterodyne receiver exhibits a conversion gain of 17.23dB, noise figure of 8.94dB, input P1dB –26.5dBm, IIP3 of –18.9dBm and image rejection of 56dB. The power consumption of the CMOS receiver is 21.6mW at 1.8V. For digital modulation measurements, a 2440MHz 802.11b 11Mbps CCK and 802.11g 54Mbps OFDM signal are applied to the receiver. The measured EVM is 5.54%(CCK) and 2.2% (OFDM). The 2.4GHz CMOS differential PA exhibits a gain of 12.6dB and output P1dB of 19dBm with PAE 14.2%.
The other part of the thesis is the development of a 5.7 GHz current reuse LNA and mixer for IEEE 802.11a receiver in a TSMC 0.25mm CMOS process. The RF is from 5.725 to 5.825GHz and the IF is at 480MHz. The LNA exhibits a noise figure of 4.5dB, linear gain of 10dB, input P1dB -2dBm and IIP3 of 6.38dBm. The mixer exhibits a noise figure of 11.78dB, conversion gain of 11.78dB, input P1dB -5dBm and IIP3 of 1.57dBm. The 5.7GHz CMOS receiver RF front-end exhibits a conversion gain of 16dB, noise figure of 6.25dB, input P1dB –21dBm, IIP3 of –11.7dBm and image rejection of 59.4dB. For digital modulation measurements, a 5750MHz 802.11a 54Mbps OFDM signal are applied to the receiver. The measured EVM is 1.43%.

第一章緒論
1 論文簡介............................................................................................. 1
2 系統規劃............................................................................................. 3
第二章5GHz CMOS 低雜訊放大器(UMC 0.18μm)
1 簡介..................................................................................................... 5
2 雜訊指數(Noise Figure : NF)............................................................... 5
2.1 雜訊指數(因素)的定義.............................................................. 5
2.2 串接雜訊因數(cascade noise factor) ........................................... 6
3 CMOS 低雜訊放大器原理................................................................. 7
3.1 共軛雜訊匹配法......................................................................... 7
3.2 CMOS 低雜訊放大器雜訊模型................................................. 9
3.3 CMOS 雜訊模型與等效雜訊變數的對應............................... 11
3.4 最佳電晶體寬度選擇............................................................... 14
3.5 共軛雜訊匹配法與最佳電晶體寬度選擇的比較................... 18
3.6 共閘極電晶體對整體雜訊指數的影響................................... 18
3.7 兩級串接放大器間的匹配對整體雜訊指數的影響............... 19
4 2.4GHz CMOS 具鏡像抑制之低雜訊放大器設計與製作............... 21
5 2.4GHz CMOS 具鏡像抑制之低雜訊放大器模擬與量測結果....... 23
6 2.4GHz CMOS 具鏡像抑制之低雜訊放大器結果討論................... 27
第三章5GHz CMOS 單端平衡混波器(UMC 0.18μm)
1 簡介................................................................................................... 28
2 CMOS 主動式混波器原理............................................................... 28
2.1 單端平衝混波器....................................................................... 28
2.2 雙端平衝混波器....................................................................... 30
2.2 CMOS 混波器雜訊模型推導................................................... 32
3 2.4GHz CMOS 雙端平衡混波器設計與製作................................... 47
4 2.4GHz CMOS 雙端平衡混波器模擬與量測結果比較................... 51
5 2.4GHz CMOS 雙端平衡混波器結果討論....................................... 55
第四章5GHz CMOS 壓控振盪器(UMC 0.18μm)
1 簡介................................................................................................... 56
2 CMOS 壓控振盪器原理................................................................... 56
2.1 LC 諧振(LC-tank)振盪器.......................................................... 57
2.2 相位雜訊(Phase Noise) ............................................................ 61
3 鎖相迴路........................................................................................... 67
3.1 鎖相迴路振盪器架構............................................................... 68
3.2 鎖相迴路之數學模型............................................................... 69
3.3 PLL 相位雜訊來源.................................................................... 74
4 應用於2.4GHz CMOS LC-tank 壓控振盪器.................................... 77
4.1 應用於2.4GHz CMOS LC-tank 壓控振盪器設計與製作........ 77
4.2 應用於2.4GHz CMOS LC-tank 壓控振盪器模擬與量測
結果比較................................................................................... 80
4.3 應用於2.4GHz CMOS L-C tank 壓控振盪器結果討論........... 84
第五章2.4GHz CMOS 差動功率放大器(UMC 0.18μm)
1 簡介................................................................................................... 85
2 功率放大器原理............................................................................... 85
2.1 負載線理論............................................................................... 87
2.2 功率等位圓............................................................................... 90
2.3 負載調整法(load pull)............................................................... 94
2.4 線性度....................................................................................... 95
3 差動功率放大器設計方法................................................................ 96
4 差動功率放大器模擬與量測............................................................ 99
5 差動功率放大器結果與討論.......................................................... 102
第六章2.4GHz CMOS 射頻前端電路整合量測(UMC 0.18μm)
1 2.4GHz 接收模組整合測試............................................................. 103
2 射頻帶通濾波器量測..................................................................... 104
3 中頻帶通濾波器量測..................................................................... 105
4 2.4GHz 接收模組整合特性量測..................................................... 107
5 2.4GHz 接收模組數位調變量測..................................................... 110
第七章5.7GHz CMOS 射頻前端電路設計及整合量測(TSMC 0.25μm)
1 簡介................................................................................................. 115
2 5.7GHz CMOS 射頻接收機架構..................................................... 115
3 5.7GHz CMOS 低雜訊放大器設計與量測..................................... 116
3.1 5.7GHz CMOS 低雜訊放大器架構......................................... 116
3.2 5.7GHz CMOS 低雜訊放大器設計流程................................. 118
3.3 5.7GHz CMOS 低雜訊放大器模擬與量測............................. 119
3.4 5.7GHz CMOS 低雜訊放大器結果討論................................. 122
4 5.7GHz CMOS 雙端平衡混波器設計與量測................................. 122
4.1 5.7GHz CMOS 雙端平衡混波器架構..................................... 122
4.2 雙端平衡混波器設計流程..................................................... 124
4.3 雙端平衡混波器模擬與量測................................................. 124
4.4 5.7GHz CMOS 雙端平衡混波器結果討論............................. 127
5 應用於5GHz 接收機之頻率合成器設計與量測.......................... 128
6 5.7GHz 接收模組整合測試............................................................. 132
6.1 Discrete 低雜訊放大器特性.................................................... 133
6.2 射頻帶通濾波器量測............................................................. 137
6.3 中頻帶通濾波器量測............................................................. 138
6.4 5.7GHz 接收模組整合特性量測............................................. 139
6.5 5.7GHz 接收模組數位調變量測............................................. 142
第八章討論.............................................................................................. 145
參考文獻...................................................................................................... 147
附錄A 1.9 GHz CMOS 頻率合成器(UMC 0.18μm)
A.1 簡介................................................................................................ 149
A.2 1.9 GHz CMOS 頻率合成器架構設計........................................... 149
A.3 系統規劃........................................................................................ 150
A.4 各級電路設計................................................................................ 150
A.4.1 相位/頻率偵測器設計與模擬............................................... 150
A.4.2 電流幫浦(charge pump) 設計與模擬................................... 153
A.4.3 除頻器(divider)設計與模擬................................................... 155
A.4.4 電壓控制振盪器與迴路濾波器............................................ 159
A.5 晶片佈局及量測結果討論............................................................ 161
                                    

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校外：2003-07-11公開

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