| 研究生: |
洪奇成 Hung, Chi-Cheng |
|---|---|
| 論文名稱: |
鑲嵌金屬導體連線銅電鍍添加劑機制及化學機械研磨後腐蝕之電化學阻抗特性研究 Investigation of Additive Mechanism on Cu Electroplating and Corrosion after Cu CMP for Damascene Interconnection Based on Electrochemical Impedance Spectroscopy |
| 指導教授: |
李文熙
Lee, Wen-Hsi 王英郎 Wang, Ying-Lang |
| 學位類別: |
博士 Doctor |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2009 |
| 畢業學年度: | 97 |
| 語文別: | 英文 |
| 論文頁數: | 205 |
| 中文關鍵詞: | 銅電鍍 、電化學 、添加劑 、腐蝕 |
| 外文關鍵詞: | Cu electroplating, Electrochemical, Additive, Corrosion |
| 相關次數: | 點閱:93 下載:20 |
| 分享至: |
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本論文主要是利用電化學阻抗的特性,經由簡單的電容、電阻、以及電感的元件所轉換組合而成的電路,進而模擬銅電鍍添加劑的電化學機制和化學機械研磨的腐蝕現象。近幾年來,多層導體連線銅鑲嵌製程已經廣泛被應用在半導體工業。由於銅電鍍技術擁有低成本、高產能、優異的填洞能力等優勢,電化學電鍍技術已經成為沉積銅導線的主要方法。早期,為了得到0.18微米,無缺陷的銅溝槽與引洞,不同的電鍍溶液成分與電鍍製程參數都已經被陸續研究與探討。目前,在0.11微米以下或是更先進90奈米製程中,有效地並精確的控制銅電鍍過程更顯得相當重要,但同時也是更加困難。在電鍍過程中,無缺陷的銅電鍍通常只在很嚴苛的製程參數下才能得到。此外,由於電鍍液通常為成分未知之商業電鍍液,而且電鍍液中的添加劑會隨著電鍍的過程裂解、變質與互相反應,所以電鍍液的電化學特性非常複雜以致於很難預測與控制。因此,改善先進65、45奈米製程良率以及銅填洞能力,銅電鍍仍需要更多的研究來釐清其電化學行為。本論文前半部份將利用電化學阻抗特性研究探討銅電鍍極化現象、經由阻抗特性轉換之等效電路,了解有機添加劑(加速劑、抑制劑)在銅電鍍的化學機制、加速劑消耗速率、加速劑與抑制劑之間的競爭關係以及裂解老化電鍍溶液對銅電鍍影響,藉由本論文的研究,期望可以達到銅膜性質與填洞能力之最佳化。
除了探討銅電鍍添加劑的化學機制外,在本文中還利用電化學阻抗特性探討銅電鍍膜在化學機械研磨後銅腐蝕的現象。在下一世代的半導體製程技術中,極低介電常數材料(介電常數小於3)將整合至銅鑲嵌製程以增加元件速度。然而,引進新材料將伴隨新的製程變數,尤其低介電常數材料其機械性質較二氧化矽為差,傳統的化學機械研磨製程容易將其損壞。並且在化學機械研磨時,常伴隨著許多缺陷的產生。最常見的有銅導線腐蝕、空洞、凹陷、微刮痕..等等。此外,由於金屬銅在化學機械研磨過程中會遇到不同材料(金屬銅/阻障層/介電層及氧化物)的移除,伽凡尼腐蝕缺陷也會產生。這些缺陷將會導致良率下降並使元件操作速度降低。本論文後半段也將利用電化學阻抗特性研究探討銅腐蝕缺陷的電化學行為,及利用等效電路了解銅氧化機制。除此之外,對於伽凡尼腐蝕缺陷也有深入探討了解,並且了解在不同條件下沉積的阻障層,將因為伽凡尼的效應,讓金屬銅/阻障層產生不一樣程度的腐蝕現象,所以藉由本論文的研究,可望達成晶圓製程上缺陷的改善效果。
In this thesis, electrochemical impedance spectroscopy (EIS) is used to transfer to the equivalent circuit being composed of simple resistor, capacitor, and inductor to study additive mechanism during copper (Cu) electroplating and corrosion after chemical mechanical polishing (CMP). Recently, Cu dual damascene for multilevel interconnection has widely been applied in semiconductor manufacturing industry. Moreover, Cu electrochemical electroplating/electrodeposition (ECP/ECD) has been the promising method for depositing dual damascene Cu fine lines in multilevel interconnection due to its low cost, high throughput and superior gap-filling capability. In early periods, to achieve defect-free filling on 0.18 μm trenches/vias, various components of plating electrolytes and electroplating process conditions were continued to investigate and study. Currently, efficiently and precisely control of Cu ECP is both essential and very difficult below 0.11μm or advanced 90 nm processes. In plating process, defect-free filling is usually obtained at a rigidly process window. Furthermore the plating chemistries are too complicated to predict and control because they are usually proprietary and they may cleave, decay and co-react during Cu ECP. Further studies are needed to realize the electrochemical behaviors of Cu ECP to improve Cu gap-filling efficiency and yield in further 65 or 45 nm. In the first half paragraph of this thesis, EIS is used to study polarization of Cu plating. The equivalent circuit transferring from EIS is used to understand the mechanism of organic additives (accelerator and suppressor) during Cu electroplating, the decomposition rate of accelerator, the competitive relationship between accelerator and suppressor, and the influence of the aging electrolyte on Cu electroplating process. It is expected to optimize the film properties and gap-filling capabilities by the research of this thesis.
In addition to the investigation of electrochemical mechanism of the additives during Cu electroplating, EIS is used to study various deposited Cu films on Cu corrosion after CMP. For next technology node, super-low-k dielectrics (k<3) will be adopted in the Cu Damascene process to reduce RC delay of interconnect. However, integrating new materials would face with many process challenges. In particular, low-k dielectrics with porous structure would be mechanically weaker than silicon dioxide. Typically CMP processes will cause sever damage on low-k films. Moreover, many and various defects will always generate after CMP processes. For example, the defects are the corrosions of Cu lines, voids, pits, and micro-scratches etc. In addition, galvanic corrosion defects occur between different materials (Cu/ barriers/ dielectric and oxides) being removed during Cu CMP process. These defects will lead to reduce the yield and to decrease the operation speeds of the devices. In the later half paragraph of this thesis, electrochemical impedance spectroscopy is also used to investigate with the electrochemical behavior and the equivalent circuit transferring from EIS is used to understand the mechanism of Cu corrosion defect. Particularly, galvanic corrosion is also deeply studied and understood. The different degree of corrosion between barrier and Cu metal has been studied on various deposited barrier due to galvanic effect. Therefore, the improvement of corrosion defect is achieved in wafer processing by the research of this thesis.
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