偏移誤差校正技術可以偵測偏移誤差電壓的量並且調整電路來消除偏移誤差，但是前景式偏移誤差校正技術只會校正一次，這樣是很難校正由溫度和供應電壓的變化所造成的偏移誤差的變化。在這篇論文提出一個偏移誤差校正電路使前置放大器和比較栓鎖器的電路能夠匹配，這意指前置放大器和比較栓所器的偏移誤差會被校正。因為此偏移誤差校正電路是由開關-電容所組成的電路，耗費的功率是比較少，而且此電路不會放在運作比較的電路交接處，因此不會影響比較的操作速度。再搭配一個新的開關網路系統，將可以實現一個背景式偏移誤差校正技術來避免偏移誤差的變化量。

此快閃式類比數位轉換器之實現是採用TSMC 0.13微米，1P8M互補型金氧半混合信號製程，模擬經過校正功能後，在1GHz的取樣頻率下，輸入訊號為480MHz時，此類比數位轉換器有36分貝的SNDR動態表現。整個晶片不包含輸出緩衝器共消耗了13.2mW的功率，FoM是259f焦耳。而大部分可以設計出來的類比數位轉換器FoM大約在0.5p到10p焦耳。

Offset calibration is a technique which detects the offset and adjusts the circuit configuration accordingly. However, foreground calibration only processes once which is not easy to prevent offset variations caused by temperature and supply voltage. In this thesis, the offset calibration circuit is proposed to make the circuit of the preamplifier and the comparator-latch match. It means that the offset voltages of the preamplifier and the comparator-latch are calibrated. Since the offset calibration circuit is based on the switch-capacitor circuit, the requirement of the power is less. The switch-capacitor circuit does not located at the connection of the conversion circuits, which does not affect the operating rate of the conversion. With the new switch network, the background offset calibration technique is implemented to prevent the offset variation.

A 6-bit 1GSample/s flash ADC is implemented by TSMC 0.13um 1P8M CMOS process. After calibration, the simulation results show that SNDR is 36dB with 480MHz input frequency at 1GHz sample rate. The power consumption is 13.2mW where output buffers are not included. FoM of this ADC is 259fJ/conversion-step. Other comparable designs have FOMs between 0.5 to 10 pJ.

[1] G. Geelen and E. Paulus, “An 8b 600 MS/s 200mW CMOS Folding A/D Converter Using an Amplifier Preset Technique,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 254–255, Feb. 2004.
[2] K. Azadet et al., “Equalization and FEC Techniques for Optical Transceivers,” in IEEE J. Solid-State Circuits, vol. 37, no. 3, pp. 317–327, Mar. 2002.
[3] R. Taft, C. Menkus, M. R. Tursi, O. Hidri, and V. Pons, “A 1.8V 1.6 GS/s 8b Self-Calibrating Folding ADC with 7.26 ENOB at Nyquist Frequency,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 252–253, Feb. 2004.
[4] K. Poulton, R. Neff, B. Setterberg, B. Wuppermann, T. Kopley, R. Jewett, J. Pernillo, C. Tan, and A. Montijo, “A 20 GS/s 8b ADC with a 1 MB Memory in 0.18um CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 318–319, Feb. 2003.
[5] X. Jiang, Z. Wang, and M. F. Chang, “A 2 GS/s 6b ADC in 0.18um CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 322–323, Feb. 2003.
[6] M. Choi and A. A. Abidi, “A 6-b 1.3-Gsample/s A/D Converter in 0.35-um CMOS,” in IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1847–1858, Dec. 2001.
[7] B. M. Min, P. Kim, F. W. Bowman III, D. M. Boisvert, and A. J. Aude, “A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC, ” in IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2031–2039, Dec. 2003.
[8] B. Murmann and B. E. Boser, “A 12-bit 75-MS/s Pipelined ADC Using Open-Loop Residue Amplification,” in IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2040–2050, Dec. 2003.
[9] B. Razavi and B. A. Wooley, “Design Techniques for High-Speed, High Resolution Comparators,” in IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1916-1926, Dec. 1992.
[10] K. Kattmann and J. Barrow, “A Technique for Reducing Differential Nonlinearity Errors in Flash A/D Converters,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 170-171, Feb. 1991.
[11] H. Kimura, A. Matuszawa, T. Nakamura, and S. Sawada, “A 10-b 300-MHz Interpolated-Parallel A/D Converter,” in IEEE J. Solid-State Circuits, vol. 28, pp. 438-446, Apr. 1993.
[12] K. Uyttenhove and M. S. J. Steyaert, “Speed-Power-Accuracy Tradeoff in High-Speed CMOS ADCs,” in IEEE Transactions on Circuits And Systems II-Analog And Digital Signal Processing, vol. 49, no. 4, pp. 280-287, Apr. 2002.
[13] T. C. William, “A 10-bit, 100MS/s A/D Converter using Folding, Interpolation, and Analog Encoding,” Ph.D. dissertation, UCLA, Dec. 1993
[14] C. A. Gobet and A. Knob, “Noise Analysis of Switched Capacitor Networks,” in IEEE Transaction on Circuits and Systems, vol. 30, no. 1, pp. 37-43, Jan. 1983
[15] C. W. Hsu, “A 6-Bit Flash A/D Converter with New Design Techniques,” Master thesis, NCKU, 2002
[16] M. B. Choi, “A 6-bit 1.3GSample/s A/D Converter in 0.35um CMOS,” Ph.D. dissertation, UCLA, 2002
[17] M. J. M. Pelgrom, A. Duinmaijer, and A. Welbers, “Matching Properties of MOS Transistor,” in IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1433–1439, Oct. 1989
[18] Ardie G. W. Venes and Rudy J. van de Plassche, “An 80-MHz, 80-mW, 8-b CMOS Folding A/D Converter with Distributed Track-and-Hold Preprocessing,” in IEEE J. Solid-State Circuits, vol. 31, no. 12, pp. 1846–1853, Dec. 1996
[19] S. S. Awad, “Analysis of Accumulated Timing-Jitter in the Time Domain,” in IEEE J. Solid-State Circuits, vol. 47, no. 1, pp. 69–73, Feb. 1998
[20] R. V. D. Plassche, “CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters 2nd Edition”, Kluwer Academic, U.S.A, 2003
[21] T. C. William, “A 10-bit 100MS/s A/D Converter using Folding, Interpolation, and Analog Encoding”, PhD. Thesis UCLA, Dec. 1993.
[22] J. Doernberg, P. R Gray and D. A. Hodges, “A 10-Bit 5-Msample/s CMOS Two-Step Flash ADC,” in IEEE J. Solid-State Circuits, vol. SC-24, no. 9, pp. 241–249, Apr. 1998
[23] J. Doernberg, P. R. Gray and D. A. Hodges, “A 10-bit 5-Msample/s CMOS Two-Step Flash ADC,” in IEEE J. Solid-State Circuits, vol. 24, no. 1, pp. 241–249, Apr. 1989.
[24] K. Uyttenhove, J. Vandenbussche, E. Lauwers, G. E. Gielen, and M. S. J. Steyaert, “Design Techniques and Implementation of an 8-bit 200-MS/s Interpolating/Averaging CMOS A/D Converter,” in IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 483–494, Mar. 2003.
[25] G. M. Yin, F. Op't Eynde, and W. Sansen, “A High-Speed CMOS Comparator with 8-b Resolution,” in IEEE J. Solid-State Circuits, vol. 27, no. 2, pp. 208–211, Feb. 1992.
[26] T. Wakimoto, Y. Akazawa, and S. Konaka, “Si Bipolar 2-GHz 6-bit Flash A/D Conversion LSI,” in IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 1345–1350, Dec. 1988.
[27] Declan Dalton et al., “A 200MSPS, 6-Bit Flash ADC in 0.6-um CMOS,” in IEEE J. Solid-State Circuits, vol. 45, no. 11, pp. 1433–1444, Dec. 1998.
[28] Akira Matsuzawa et al., “A 6b 1GHz Dual-Parallel A/D Converter,” in IEEE Int. Solid-State Circuits Conf., pp. 174–175, Feb. 1991.
[29] I. Megr and D. Dalton, “A 500M-Sample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read Channel Applications,” in IEEE J. Solid-State Circuits, vol. 24, pp. 1587–1597, Dec. 1989.
[30] S. Tsukamoto, W. G. Schofield and T. Endo, “A CMOS 6-b 400M-Sample/s ADC with Error Correction,” in IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1939–1947, Dec. 1998.
[31] V. Srinivas, S. Pavan, A. Lachhwani, and N. Sasidhar, “A Distortion Compensating Flash Analog-to-Digital Conversion Technique”, in IEEE J. Solid-State Circuit, vol. 4, no.9, pp.1959-1969, Sep. 2006.
[32] P. M. Figueiredo and J. C. Vital, “Kickback Noise Reduction Techniques for CMOS Latched Comparators”, in IEEE Transactions on Circuits and Systems II, vol. 53, no. 7, pp.541-545, July 2006.
[33] P. M. Figueriedo, P. Cardoso, A. Lopes, C. Fachada, N. Hamanishim, K. Tanabe, and J. Vital, “A 90nm CMOS 1.2V 6b 1GS/s Two-Step Subranging ADC”, in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 2320–2329, Feb. 2006.
[34] Y. Tamba, and K. Yamakido, “A CMOS 6b 500MSample/s ADC for a Hard Disk Drive Read Channel”, in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 324–325, Feb. 1999.
[35] K. Uyttenhove and M. S. J. Steyaert, “A 1.8-V 6-Bit 1.3-GHz Flash ADC in 0.25-um CMOS”, IEEE J. Solid-State Circuit, vol. 38, no.7, pp.1115-1122, July 2003.