由於近年來多媒體影像解析度不斷提升，使得影像壓縮技術受到極大的注視，且多種壓縮標準(如MPEG-2、H.264/AVC等)亦相繼提出，若要針對不同的視訊標準重新開發各自的編解碼系統，無疑是延遲產品開發上市時程。本論文主要針對此一問題，針對不同的應用需求開發了三種熵編解碼電路。首先，我們開發了一高速內容適應性二位元算數編碼(CABAC)器，於開發初期分析不同的視訊資料所產生的資料量分布狀況，之後僅針對某些特定語法結構元素才採用每一時脈週期處理兩筆資料之處理方式，來達到付出極少硬體成本就可明顯改善輸出率的目標。相較於現今其他不支援多符號(multi-symbol)的編碼器，所開發之電路在增加不到25%的硬體成本達到近兩倍的運算速度傳輸率。最後兩種所開發之積體電路設計皆為熵解碼電路，其一，本論文利用粗顆粒(coarse-grain)可重組架構來有效合併內容適應性二位元算數編碼與內容適應性可變長度編碼(CAVLC)兩種熵解碼器電路，根據實驗結果顯示，採用可重組化元件架構後可以節省1.5 K的邏輯閘，除此之外，只要增加相當有限的硬體面積，就可以利用可重組化元件陣列閒置的時間去執行反轉換(inverse transform)運算，而所開發之電路可以在工作頻率66 MHz時即時解碼Baseline/Main profile Level 3.0條件下的影像串流。其二，本論文提出將可變長度編碼之樹狀結構做切割，之後利用附屬樹分類(sub-tree classification)的方式來減少MPEG-2和H.264所需儲存之字元，而解碼速度上亦能有大幅提升。由實驗結果可以得知，所開發之 H.264/AVC可變長度解碼器在200 MHz操作頻率下其電路面積為 6.23 K個邏輯閘。而所提出來的MPEG-2/H.264解碼器架構在180 MHz操作頻率下其電路面積為 11.9 K個邏輯閘，比起單獨的H.264與MPEG-2解碼器合起來的結果，更可降低20%的硬體面積。最後，針對SOCLE CDK平台，本論文利用所開發之影像編解碼元件資料庫（包含已開發之三個熵編解碼器和其他相關元件）與架構映射演算法設計出支援MPEG-2和H.264/AVC影像解碼系統。

Ever increasing video resolution has made video compression technology increasingly important. Many standards (such as MPEG-2 and H.264/AVC) have been proposed for various video applications. Customizing systems for each application would increase development time and thus delay time-to-market. To solve this problem, this dissertation developed three entropy encoder/decoder circuits for different target multimedia system. First, a high throughput encoder for context-based adaptive binary arithmetic coding (CABAC) is proposed. By analyzing the distribution of binarized bins in various video sequences, this work improves the encoding rate with limited hardware overhead by allowing only a certain type of syntax element to be processed two bins at a time. Compared with related works that do not support multi-symbol encoding, the proposed method can achieve nearly twice their throughput rate with hardware overhead of below 25%. Second, we combined the two entropy decoding methods, context-based variable length coding (CAVLC) and CABAC, defined in the H.264 standard using a coarse-grain reconfigurable architecture. Experimental results show that about 1.5K gates can be eliminated. Besides, using the idle time in reconfigurable cell arrays, the base cell can be extended to carry out the inverse transform with very limited overhead. The proposed entropy decoder design, which operates at 66 MHz, can decode video sequences for Baseline and Main profiles at Level 3.0. Third, each VLC tree in MPEG-2 and H.264/AVC is decomposed using sub-tree (ST) classification. The developed tree partitioning with ST classification method can greatly improve hardware reuse for a multi-standard VLC decoder design. The gate count of the proposed H.264/AVC context-based variable length decoder design is 6.23K when synthesized to operate at 200 MHz, and that of the proposed MPEG-2/H.264 VLC decoder is 11.9K when synthesized to operate at 180 MHz. The gate count of combined VLC decoder is 20% lower than the sum of the areas of individual H.264 and MPEG-2 VLC decoders. Finally, based on the database (including the three entropy coders and other pre-designed components), the proposed architecture mapping algorithm is used to find a suitable solution to support MPEG-2 and H.264/AVC video decoding on the SOCLE CDK platform.

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