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研究生： 黃嘉俊
Huang, Chia-Chun
論文名稱： 使用無負載延伸計數技術之增量型類比至數位轉換器設計
Design of an Incremental Analog-to-Digital Converter with Loading-Free Extended Counting Technique
指導教授： 劉濱達
Liu, Bin-Da
林家民
Lin, Jai-Ming
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2012
畢業學年度： 100
語文別： 英文
論文頁數： 71
中文關鍵詞： 無負載延伸計數技術 、增量型三角積分調變器 、連續漸進式轉換器 、類比至數位轉換器
外文關鍵詞： Loading-free extended counting architecture, incremental sigma-delta modulator, successive approximation register, analog-to-digital converter
相關次數： 點閱：107  下載：3 
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    • 本論文提出基於增量型類比至數位轉換器之無負載延伸計數架構，並結合具有高使用效率特性的連續漸進式類比至數位轉換器。本論文設計解析度為十二位元之轉換器，其中包括解析最大有效位元的充電幫浦增量型轉換器和解析最小有效位元的同步連續漸進式轉換器，而且無需額外校正機制。此轉換電路使用連續漸進式轉換器來完成延伸轉換，透過所提出的無負載延伸計數架構，增量型轉換器中的積分器並不需要連續漸進式轉換器的電容陣列來作為儲存殘值的負載，如此即能放寬放大器所需要的規格。增量型轉換器及連續漸進式轉換器採用平行方式處理，可減少電路轉換時間。電路以TSMC 0.18-μm 1P6M CMOS製程來模擬設計，在訊號頻寬為2 kHz和供應電壓為1.8 V環境下，此轉換器之SNDR可達到69.38 dB，功率消耗僅為23.07 μW。

    In this thesis, the loading-free extended counting architecture based on incremental ADC that uses SAR modulator to take an advantage of power efficiency is proposed. This work adopts a charge-pump incremental ADC to convert the first 5-bit MSB and a synchronous SAR modulator to convert the last 7-bit LSB, and thus totally 12-bit resolution can be obtained without calibration. The SAR ADC is used to complete the extended conversion, but with the proposed architecture the residual error integrator of the counting converter is not loaded by the DAC capacitor array of SAR modulator, which means the operational amplifier design can be relaxed. Since the used incremental ADC and SAR modulator are operated in parallel, total conversion time of this ADC can be reduced. The proposed converter is implemented in TSMC 0.18-μm 1P6M CMOS technology. Under 2-kHz input signal bandwidth and 1.8-V power supply, the simulated peak SNDR of 69.38 dB is achieved with only 23.07-μW power consumption.

    Abstract (Chinese) i Abstract (English) iii Acknowledgement v Table of Contents vii List of Figures xi List of Tables xiii Chapter 1 Introduction 1 1.1 Motivation and Introduction 1 1.2 Research Procedure 4 1.3 Thesis Outline 4 Chapter 2 Fundamental Concepts of Analog-to-Digital Converter 7 2.1 Analog-to-Digital Conversion 7 2.1.1 Quantization error 8 2.1.2 Nyquist-rate conversion 9 2.1.3 Oversampling conversion 10 2.2 Sigma-Delta Modulators 10 2.3 Incremental Sigma-Delta Modulators 12 2.4 Successive Approximation Register Modulators 15 2.5 Extended Counting Technique 17 2.6 Summary 20 Chapter 3 Design of an Incremental ADC with Loading-Free Extended Counting Architecture 21 3.1 Sample-Hold Amplifier 22 3.1.1 Single-to-differential sample-hold amplifier 23 3.1.2 Bootstrapped switch 24 3.1.3 Simulation results 25 3.2 Incremental ADC with charge-pump technique 27 3.2.1 Charge-pump technique 27 3.2.2 Decimation filter 30 3.2.3 Simulation results 30 3.3 Successive Approximation Register ADC 32 3.3.1 Capacitor array 33 3.3.2 DAC control logic 34 3.3.3 Timing control logic 35 3.3.4 Simulation results 36 3.4 Loading-Free Extended Counting Architecture 38 3.4.1 Extended counting with loading-free 39 3.4.2 Parallel operation 40 3.5 Summary 42 Chapter 4 Experimental Results and Comparison 43 4.1 Circuit Implementation 44 4.1.1 Two-stage operational amplifier with Miller compensation 44 4.1.2 Dynamic Comparator 49 4.1.3 Controlling clock phases 51 4.2 Simulation Results 52 4.2.1 Layout 52 4.2.2 Simulation results 54 4.2.3 Comparison and discussion 57 4.3 Measurement Results 58 4.3.1 Measurement environment 59 4.3.2 Measurement results and discussion 61 Chapter 5 Conclusions and Future Work 63 5.1 Conclusions 63 5.2 Future Work 64 References 67

    [1] Y. Gao, Y. Zheng, S. Diao, W. D. Toh, C. W. Ang, M. Je, and C. H. Heng, “Low-power ultrawideband wireless telemetry transceiver for medical sensor applications,” IEEE Trans. Biomed. Eng., vol. 58, pp. 768-772, Mar. 2011.
    [2] Y. L. Tsou and S. Berber, “Design, development and testing of a wireless sensor network for medical applications,” in Proc. IEEE Int. Conf. Wireless Commun. Mobile Comput., July 2011, pp. 826-830.
    [3] P. Kumar, S. G. Lee, and H. J. Lee, “A user authentication for healthcare application using wireless medical sensor networks,” in Proc. IEEE Int. Conf. High Performance Comput. and Commun., Sept. 2011, pp. 647-652.
    [4] J. Zhang, “Research on embedded fingerprint identification system,” in Proc. IEEE Int. Conf. Mechanic Autom. and Contr. Eng., July 2011, pp. 594-597.
    [5] S. Zhou and X. Lu, “Fingerprint identification and its applications in information security fields,” in Proc. IEEE Int. Conf. Inf. Sci. and Manag. Eng., Aug. 2010, pp. 97-99.
    [6] A. Stelzer, R. Feger, and M. Jahn, “Highly-integrated multi-channel radar sensors in SiGe technology for automotive frequencies and beyond,” in Proc. IEEE Conf. ICECom, Sept. 2010, pp. 1-11.
    [7] J. P. Carmo, P. M. Mendes, C. Couto, and J. H. Correia, “A 2.4-GHz CMOS short-range wireless-sensor-network interface for automotive applications,” IEEE Trans. Ind. Electron., vol. 57, pp. 1764-1771, May 2010.
    [8] F. N. Murrieta R, O. Y. Sergiyenko, V. V. Tyrsa, D. Hernández B, and W. Hernandez, “Frequency domain automotive sensors: resolution improvement by novel principle of rational approximation,” in Proc. IEEE Int. Conf. Ind. Technol., Mar. 2010, pp. 1313-1318.
    [9] D. Liu, S. Yin, J. Chen, H. Gao, and S. Wei, “A portable environmental monitoring system based on WSN for off-the-shelf sensors,” in Proc. IEEE Int. Conf. Computational Problem-Solving, Oct. 2011, pp. 1-4.
    [10] K. T. Tang, S. W. Chiu, H. C. Hao, S. C. Wei, T. H. Lin, C. M. Yang, D. J. Yao, and W. C. Yeh, “An electronic-nose sensor node based on polymer-coated surface acoustic wave array for environmental monitoring,” in Proc. IEEE Int. Conf. Green Circuits and Syst., June 2010, pp. 118-122.
    [11] C. Oliveira and G. Gonçalves, “Environmental monitoring services and wireless sensor networks applied on urban spaces,” in Proc. IEEE Int. Conf. Autom. Quality and Testing Robot., May 2010, pp. 1-6.
    [12] B. Razavi, Design of Analog CMOS Integrated Circuits. Boston, MA: McGraw-Hill, 2001.
    [13] P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design. New York: Oxford, 2002.
    [14] D. A. Johns and K. Martin, Analog Integrated Circuit Design. New York: John Wiley & Sons, 1997.
    [15] R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters. New York: IEEE Press, 2005.
    [16] S. R. Norsworthy, R. Schreier, Gabor C. Temes, Delta-Sigma Data Converters: Theory, Design, and Simulation. New York: IEEE Press, 1997.
    [17] J. Markus, J. Silva, and G. C. Temes, “Theory and applications of incremental ΔΣ converters,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, pp. 678-690, Apr. 2004.
    [18] P. Rombouts, W. De Wilde, and L. Weyten, “A 13.5-b 1.2-V micropower extended counting A/D converter,” IEEE J. Solid-State Circuits, vol. 36, pp. 176-183, Feb. 2001.
    [19] J. De Maeyer, P. Rombouts, and L. Weyten, “A double-sampling extended-counting ADC,” IEEE J. Solid-State Circuits, vol. 39, pp. 411-418, Mar. 2004.
    [20] A. Agah, K. Vleugels, P. B. Griffin, M. Ronaghi, J. D. Plummer, and B. A. Wooley, “A high-resolution low-power incremental ΣΔ ADC with extended range for biosensor arrays,” IEEE J. Solid-State Circuits, vol. 45, pp. 1099-1110, June 2010.
    [21] P. Y. Wu, V. S. L. Cheung, and H. C. Luong, “A 1-V 100-MS/s 8-bit CMOS switched-opamp pipelined ADC using loading-free architecture,” IEEE J. Solid-State Circuits, vol. 42, pp. 730-738, Apr. 2007.
    [22] S. Rabii and B. A. Wooley, The Design of Low-Voltage, Low-Power Sigma-Delta Modulators. Boston, MA: Kluwer Academic, 1999.
    [23] B. P. Brandt and B. A. Wooley, “A 50-MHz multibit sigma-delta modulator for 12-b 2-MHz A/D conversion,” IEEE J. Solid-State Circuits, vol. 26, pp. 1746-1756, Dec. 1991.
    [24] Y. Matsuya, K. Uchimura, A. Iwata, T. Kobayashi, M. Ishikawa, and T. Yoshitome, “A 16-bit oversampling A-to-D conversion technology using triple-integration noise shaping,” IEEE J. Solid-State Circuits, vol. 22, pp. 921-929, Dec. 1987.
    [25] R. W. Knepper, “Dynamic depletion mode: an E/D MOSFET circuit method for improved performance,” IEEE J. Solid-State Circuits, vol. 13, pp. 542-548, Oct. 1978.
    [26] J. Robert and P. Deval, “A second-order high-resolution incremental A/D converter with offset and charge injection compensation,” IEEE J. Solid-State Circuits, vol. 23, pp. 736-741, June 1988.
    [27] O. J. A. P. Nys and E. Dijkstra, “On configurable oversampled A/D converters,” IEEE J. Solid-State Circuits, vol. 28, pp. 736-742, July 1993.
    [28] V. Quiquempoix, P. Deval, A. Barreto, G. Bellini, J. Markus, J. Silva, and G. C. Temes, “A low-power 22-bit incremental ADC,” IEEE J. Solid-State Circuits, vol. 41, pp. 1562-1571, July 2006.
    [29] A. Nilchi and D. A. Johns, “Charge-pump based switched-capacitor integrator for DS modulators,” Electron. Lett., vol. 46, pp. 400-401, Mar. 2010.
    [30] C. C. Liu, S. J. Chang, G. Y. Huang, and Y. Z. Lin, “A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure,” IEEE J. Solid-State Circuits, vol. 45, pp. 731-740, Apr. 2010.
    [31] G. Y. Huang, C. C. Liu, Y. Z. Lin, and S. J. Chang, “A 10-bit 12-MS/s successive approximation ADC with 1.2-pF input capacitance,” in Proc. IEEE Asian Solid-State Circuits Conf., Nov. 2009, pp. 157-160.
    [32] L. Rossi, S. Tanner, and P. A. Farine, “A 16-bit, 150-uW, 1-KS/s ADC with hybrid incremental and cyclic conversion scheme,” in Proc. IEEE Int. Conf. Electron., Circuits and Syst., Dec. 2009, pp. 751-754.
    [33] Agilent Technologies. [Online]. Available: http://www.home.agilent.com/agilent/home.jspx

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