Content 摘要 ii Abstract iii Content iv Figure captions v Table captions x Chapter 1 Background 1 1.1 Power Consumption issue in Advanced CMOS 1 1.2 Subthreshold Swing Definition 3 1.3 Sub-60 Devices 4 1.3.1 Feedback FETs (FBFETs) 4 1.3.2 Superlattice MOSFET (SL-MOSFET) 5 1.3.3 Impact Ionization FETs (IMOS) 5 1.3.4 Nano Mechanical FETs (NEMFETs) 6 1.3.5 Tunnel FETs (TFETs) 6 1.3.6 Ferroelectric gate dielectric FET (NC-FET) 7 Chapter 2 Literature Review 8 2.1 Negative capacitance theory derivation and modeling 8 2.2 Negative capacitance device manufacturing 19 2.3 Introduction to the characteristics of a ferroelectric material 31 Chapter 3 Introduction to the TCAD Setting 36 3.1 Introduction to the device structure 36 3.2 the TCAD ferroelectric model before version 2017.09 38 3.3 TCAD version 2017.09 (L-K equation) 40 Chapter 4 Simulation Results and Discussion 43 4.1 A simulation of a ferroelectric MIS structure 43 4.2 The P-V curve least square fitting extracts the FE parameter 45 4.2 Device structure and simulation parameters 47 4.3 The gate stack capacitance analysis of NC-FET 48 4.5 Negative Capacitance Impact versus Channel Length 51 4.6 Impact of drain bias on negative capacitance 59 Chapter 5 63 Conclusions 63 Chapter6 64 Question and Answer 64 Prof. Kao: 64 Prof. Lin: 64 Prof. Chu: 65 Chapter 7 66 References 66 Appendix 69 Figure captions Fig. 1.1 Schematic log Id-Vg characteristics showing the factors affecting power consumption [1]. 2 Fig. 2.1. (a) The energy landscape of a negative capacitor. (b) The energy landscape of a typical capacitor [13]. 8 Fig. 2.2. An energy dynamic energy state diagram of a ferroelectric capacitor showing the transient analysis [14]. 9 Fig. 2.3. Schematic of a ferroelectric/dielectric bi-layer [15]. 10 Fig. 2.4. An ordinary capacitor with the right amount of capacitance can stabilize a ferroelectric material where its capacitance is negative [15]. 11 Fig. 2.5. The broken line shows the negative dP/dE region that is normally unstable but is effectively stabilized when placed in a series with a normal capacitor [16]. 12 Fig. 2.6. A simple NC-FET structure. The insulator is a ferroelectric material [16]. 13 Fig.2.7. The surface potential amplification versus the ferroelectric layer thickness [16]. 14 Fig. 2.8. (a) A schematic of a P-E curve and a channel load line as a function of Vg. A cross point of these two curves is the static operational point of the NCFET. (b) Demonstrates the operational points (i), (ii), and (iii) represents low, middle, and high Vg, respectively. The corresponding band diagrams in (b) [17]. 15 Fig. 2.9. Id versus VGS for various TFEs of the NCFET [18]. 16 Fig. 2.10. CFE and CMOS. Internal gate voltage VMOS is amplified over VG by CFE/(CFE-CMOS). CFE has to be close to CMOS [19]. 17 Fig. 2.11. A 5.8nm FE film brings CFE closer to CMOS (see Fig. 2-10) and reduces V DD. A 7nm FE film causes hysteresis because CFE crosses CMOS [19]. 17 Fig. 2.12. P-E characteristics (a-i) at fixed Ec and variable Pr and (a-ii) at fixed Pr and variable Ec. (b-i and ii) Id-Vg characteristics of NCFETs corresponding to the P-E characteristics [17]. 18 Fig. 2.13. The schematic structure of an NC-FinFET with an internal gate [20]. 19 Fig. 2.14. The graphic process flow of NC-FinFET [20]. 20 Fig. 2.15. The more details about the process flow. [20]. 20 Fig. 2-16 (a) The TEM picture of the planar HfZrO capacitor and (b) the gate-stack structure of an NC-FinFET [20]. 21 Fig. 2.17. IV measurement on a planar capacitor extracts the FE polarization. [20]. 21 Fig. 2.18 The Id-Vg curve of an internal gate FinFET (conventional FinFET). 22 Fig. 2.19. The Id-Vg curve of an external gate NC-nFET [20] 22 Fig. 2.20 The HZO has better ferroelectric characteristic after higher temperature annealing because the high temperature makes thin film form the orthorhombic face easily [20]. 23 Fig. 2.21. Id-Vg curve of N-type NC-FinFET and internal FinFET with 600C annealing [20]. 24 Fig. 2.22. Comparison of subthreshold swing, SS, for N-type NC-FinFET and internal FinFET [20]. 24 Fig. 2.23. 25 Fig. 2.24. Comparison of subthreshold swing, SS, for P-type NC-FinFET and internal FinFET [20]. 25 Fig. 2.25. Gate leakage versus capacitance equivalent thickness. The right corner graph demonstrates the I-V curve of a 1.5-nm-thick ferroelectric HZO [20]. 26 Fig.2.26. (a) Cross-sectional TEM of FEHZO with ~1.5 nm and 1-2 monolayer SiO2. (b) C-V of the MIS structure [20]. 27 Fig. 2.27. Id-Vg curve of 1.5-nm-thick ferroelectric HZO gate-stack FETs after RTA process at 700°C. The SSmin = 52 mV/dec [20]. 27 Fig. 2.28. Capacitance versus Q of Si MOS and 1.5, 3, and 5nm-thick FE-HZO. The capacitances are extracted by the L-K model [21]. 28 Fig. 2.29. Transfer characteristics (IDSVGS) of FEHZO FETs with 3, 5, and 7 nm gate-stack thin film with RTA at 700°C. The thinner FE-HZO film can improve hysteresis [21]. 29 Fig. 2.30. SS and hysteresis window (ΔVT) versus FEHZO thickness. The 1.5-nm-thick ferroelectric HZO can achieve the goal of both SS < 60mV/dec and less hysteresis [21]. 29 Fig. 2.31. Simulated fast sweep IDSVGS of a 1.5nm FE-HZO gate-stack FET as the sweeping frequency increase the hysteresis also increase [21]. 30 Fig .2.32. Calculated hysteresis versus. sweep time for a 1.5-nm-thick gate-stack ferroelectric HZO with Vds=0.5V [21]. 31 Fig. 2.33. shows different component of 9nm HZO thin film which has different ferroelectric characteristic. The pure HfO2 thin film shows paraelectric characteristic. The pure ZrO2 has antiferroelectric characteristic. [25]. 32 Fig. 2.34.HZO Polarization loops with (a) as-deposited shows para-electric type for a linear polarization, (b) 450 ◦C annealing shows the FE type, (c) 600 ◦C annealing shows the AFE type, and (d) 800 ◦C annealing becomes resistant due to high leakage. [27]. 33 Fig. 2.35. Schematic of (a) paraelectric, (b) ferroelectric, (c) anti-ferroelectric, and (d) ferroelectric behavior according to the electron leakage path [27]. 34 Fig. 2.36. Energy landscape (U-P) and its derivative (dU/dP) of HZO thin film with (a) as-deposited, (b) 450◦C, and (c) 600◦C. Note that the free energy is extracted from the P-E curve and is based on Landau–Khalatnikov (LK) equations. The dU/dP of AFE HZO (600◦C) exhibits a localized negative slope and indicates the existence of the NC component [27] 34 Fig. 3.1. (a) The simulated three-dimensional NC double gate Fin-FET with variable channel lengths Lc (100 nm ~ 25nm). Fin width Wfin=15nm; fin height Hfin =30nm. (b) A schematic diagram of the gate- stack structure. 36 Fig. 4.1. The MIS structure and the setting of the ferroelectric physical mechanism implemented as the code on the right hand side 43 Fig. 4.2. The Q-V curve of the MIS structure. The black line represents the FE layer with the ferroelectric mechanism. The red line represents the FE layer without the ferroelectric mechanism. 44 Fig.4.3. The least square fitting result 46 Fig. 4.5. Equivalent circuit for the gate-stack and channel capacitance, Ctotal represents the total gate capacitance considering CFE. 48 Fig. 4.6. The gate C-V curve simulation result for gate stacks with three different interfacial oxide thicknesses. The same symbol type corresponds to the same interfacial oxide thickness. The solid symbols are C-V with negative capacitance effects; the hollow symbols are C-V without considering CFE by intentionally switching off ferroelectric polarization in TCAD. 50 Fig.4.7. Graph of 1/Ctotal versus 1/Cox for three different oxide thickness conditions. CFE. is extracted based-on the inverse of the extrapolated y-intercept of this curve (-6.2554x 10-17 F). Vg=1.0V 50 Fig. 4.8. (a) The Id-Vg curve comparison at a channel length of 100nm 51 Fig. 4.9. (b) The Id-Vg curve comparison at a channel length of 90nm 51 Fig. 4.10. (c) The Id-Vg curve comparison at a channel length of 80nm 51 Fig. 4.11. (d) The Id-Vg curve comparison at a channel length of 70nm 52 Fig. 4.12. (e) The Id-Vg curve comparison at a channel length of 60nm 52 Fig. 4.13. (f) The Id-Vg curve comparison at a channel length of 50nm 52 Fig. 4.14. (g) The Id-Vg curve comparison at a channel length of 40nm 53 Fig. 4.15. (h) The Id-Vg curve comparison at a channel length of 30nm 53 Fig. 4.16. (i) The Id-Vg curve comparison at a channel length of 25nm 53 Fig. 4.17. Subthreshold swing versus channel length, with and without turning on ferroelectric polarization effects in TCAD. The percentage decrease in the subthreshold swing is labeled and pointed out using broken blue arrows. 54 Fig.4.18. The schematic equivalent capacitance component model considering the drain capacitance 55 Fig. 4.19. Calibration result for SS as function of channel length. The TCAD data is the same as that in Fig. 4.7 The blue and red lines are model predictions. 57 Fig. 4.20. The ion versus the channel length 58 Fig. 4.21. (a) The impact of different applying drain biases at Lc =100nm with and without FE polarization 59 Fig. 4.21. (b) The impact of different applying drain biases at Lc =90nm with and without FE polarization 59 Fig. 4.21. (c) The impact of different applying drain biases at Lc =80nm with and without FE polarization 60 Fig. 4.21. (d) The impact of different applying drain biases at Lc =70nm with and without FE polarization 60 Fig. 4.21. (e) The impact of different applying drain biases at Lc =60nm with and without FE polarization 60 Fig. 4.21. (f) The impact of different applying drain biases at Lc =50nm with and without FE polarization 61 Fig. 4.21. (g) The impact of different applying drain biases at Lc =40nm with and without FE polarization 61 Fig. 4.21. (g) The impact of different applying drain biases at Lc =30nm with and without FE polarization 61 Fig. 4.21. (g) The impact of different applying drain biases at Lc =25nm with and without FE polarization 62 Table captions Table 4.1 The NC-FinFET parameter used in the TCAD simulation 47