本篇論文提出一種新穎的自我測試架構，能結合確定性掃描測試和低成本內建自我測試的優點。我們提出兩種通過修改掃描單元以在掃描鍊結構中記錄測試資料的電路設計。所提出的測試資料記錄設計允許在響應移出同時提取下一筆測試資料，然後我們再將測試資料重建為壓縮的確定性測試向量並進行電路測試。配合所開發的新測試流程，與先前的設計相比能將測試週期減少接近一半。我們也改進測試解壓縮器的架構，通過並行輸入設定資料以減少測試週期。此外，我們在修改後的掃描單元的基礎下提出一種低成本未知值容忍掃描鍊架構來處理未知值。透過使用相應的X邊界方法，可無需大量用於屏蔽未知值的數據和電路。我們開發新的測試程序來減少測試時間。實驗結果表明，所提出的架構能夠以短測試週期和低面積開銷實現高測試覆蓋率。以有668萬邏輯閘的8核開源OpenSPARC T2處理器為例，測試覆蓋率能達到99.95%，壓縮比為935倍，且總面積開銷僅為2.02%。

This thesis presents a novel self-test architecture that combines the advantages of deterministic scan-based test and low-cost built-in self-test. We propose two novel designs that modify the scan cells to record test data in a scan chain structure. The proposed test data recording design allows the next test data to be extracted while the response is shifted out. Then, we reconstruct the test data into a compressed deterministic test pattern and apply the pattern for testing. Cooperating with a new test procedure, we reduce the test cycles by about half compared to the previous work. We also improve the test decompressor architecture, which can parallel load setup data to reduce the test cycles. Additionally, we propose a low-cost X-tolerant scan chain architecture based on the modified cells to deal with unknown values. With the corresponding X-bounding mothed, there is no need for large X-masking data and huge X-masking logic. Experimental results show that the proposed architecture can achieve high test coverage with low test cycles and low area overhead. For example, in the 8-core open-source OpenSPARC T2 processor with 6.68M gates, the test coverage is 99.95% with a compression ratio of 935x, and the total area overhead is only 2.02%.

[1] L.-T. Wang, C.-W. Wu, and X. Wen, VLSI Test Principles and Architectures: Design for Testability. Amsterdam, The Netherlands: Morgan Kaufmann, 2006, ch. 5.
[2] L.-T. Wang, C. E. Stroud, and N. A. Touba, System-on-Chip Test Architectures: Nanometer Design for Testability, Morgan Kaufmann, 2010, ch. 2.
[3] N. A. Touba, “Survey of test vector compression techniques,”IEEE Des. Test. Comput., vol. 23, no. 4, pp. 294–303, Apr. 2006.
[4] U. S. Mehta, K. S. Dasgupta, and N. M. Devashrayee, Code Based Test Data Compression for SoC Testing: Optimization of Time, Power and Area Overhead. Saarbrücken, Germany: LAP LAMBERT Academic, 2012.
[5] J. Rajski, J. Tyszer, M. Kassab, and N. Mukherjee, “Embedded deterministic test,”IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 23, no. 5, pp. 776–792, May 2004.
[6] Y. Huang, S. Milewski, J. Rajski, J. Tyszer, and C. Wang, “Low Cost Hypercompression of Test Data,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 10, pp. 2964-2975, Oct. 2020.
[7] A. Chandra, H. Yan, and R. Kapur, “Multimode Illinois Scan Architecture for Test Application Time and Test Data Volume Reduction,” in Proc. IEEE VLSI Test Symposium (VTS), 2007, pp. 84-92.
[8] S. Samaranayake, E. Gizdarski, N. Sitchinava, F. Neuveux, R. Kapur, and T. W. Williams, “A reconfigurable shared scan-in architecture,” in Proc. VLSI Test Symposium, 2003, pp. 9-14.
[9] Kapur, and Y. Kanzawa, “Scalable Adaptive Scan (SAS),” in Proc. Design, Automation & Test in Europe Conference & Exhibition, 2009, pp. 1476-1481.
[10] A. Chandra, S. Kulkarni, S. Chebiyam, and R. Kapur, “Designing efficient combinational compression architecture for testing industrial circuits,” in Proc. International Symposium on VLSI Design and Test, 2015, pp. 1-6.
[11] T. Yu, A. Cui, M. Li, and A. Ivanov, “A new decompressor with ordered parallel scan design for reduction of test data and test time,” in Proc IEEE International Symposium on Circuits and Systems (ISCAS), 2015, pp. 641-644.
[12] H. Lim, H. Yun and S. Kang, “A Hybrid Test Scheme for Automotive IC in Multisite Testing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 12, pp. 5671-5680, Dec. 2022.
[13] J. Rajski, J. Tyszer, G. Mrugalski, W. -t. Cheng, N. Mukherjee and M. Kassab, “X-Press Compactor for 1000x Reduction of Test Data,” in Proc. IEEE International Test Conference, Santa Clara, CA, USA, 2006, pp. 1-10
[14] P. Wohl, J. A. Waicukauski and S. Ramnath, “Fully X-tolerant combinational scan compression,” in Proc. IEEE International Test Conference, Santa Clara, CA, USA, 2007, pp. 1-10
[15] J. Rajski, J. Tyszer, G. Mrugalski, W. -T. Cheng, N. Mukherjee and M. Kassab, “X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 1, pp. 147-159, Jan. 2008
[16] G. Mrugalski, J. Rajski, J. Tyszer and B. Włodarczak, “X-Masking for Deterministic In-System Tests,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 42, no. 11, pp. 4260-4269, Nov. 2023
[17] P. Wohl, J. A. Waicukauski, G. A. Maston and J. E. Co“burn, “XLBIST: X-Tolerant Logic BIST,” in Proc. IEEE International Test Conference (ITC), Phoenix, AZ, USA, 2018, pp. 1-9.
[18] P. Wohl, J. Waicukauski, A. Bhat, V. K. K S and R. Karmakar, “Selective Multiple Capture Test (SMART) XLBIST,” in Proc. IEEE International Test Conference India (ITC India), Bangalore, India, 2022, pp. 1-6.
[19] B. Koenemann, “LFSR-coded test pattern for scan designs,” in Proc. Eur. Test Conf., Munich, Germany, 1991, pp. 237–242.
[20] S. Hellebrand, S. Tarnick, J. Rajski, and B. Courtois, “Generation of vector patterns through reseeding of multiple-polynomial linear feedback shift registers,” in Proc. Int Test Conf., Baltimore, MD, USA, 1992, pp. 120–129.
[21] B. Koenemann, C. Barnhart, B. Keller, T. Snethen, O. Farnsworth and D. Wheater, “A smartBIST variant with guaranteed encoding,” in Proc. Asian Test Symp., Kyoto, Japan, 2001, pp. 325–330.
[22] G. Mrugalski, J. Rajski, Ł. Rybak, J. Solecki and J. Tyszer, “A deterministic BIST scheme based on EDT-compressed test patterns,” in Proc. IEEE International Test Conference (ITC), Anaheim, CA, USA, 2015, pp. 1-8.
[23] A. -W. Hakmi, S. Holst, H. -J. Wunderlich, J. Schlöffel, F. Hapke and A. Glowatz, “Restrict encoding for mixed-mode BIST,” in Proc. IEEE VLSI Test Symp., Santa Cruz, CA, USA, 2009, pp. 179–184.
[24] G. Kiefer, H. Vranken, E. J. Marinissen, and H.-J. Wunderlich, “Application of deterministic logic BIST on industrial circuits,” J. Electron. Test. Theory Appl., vol. 17, nos. 3–4, pp. 351–362, 2001.
[25] L. Li and K. Chakrabarty, “Test set embedding for deterministic BIST using a reconfigurable interconnection network,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 23, no. 9, pp. 1289–1305, Sep. 2004.
[26] M. A. Kochte, C. G. Zoellin, and H.-J. Wunderlich, “Concurrent selftest with partially specified patterns for low test latency and overhead,” in Proc. IEEE Eur. Test Symp., Seville, Spain, 2009, pp. 53–58.
[27] Y. Li, S. Makar, and S. Mitra, “CASP: Concurrent autonomous chip self-test using stored test patterns,” in Proc. Design Autom. Test Eur., Munich, Germany, 2008, pp. 885–890.
[28] D. Xiang, X. Wen, and L.-T. Wang, “Low-power scan-based built-in self-test based on weighted pseudorandom test pattern generation and reseeding,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 25, no. 3, pp. 942–953, Mar. 2017.
[29] B. Kaczmarek, G. Mrugalski, N. Mukherjee, A. Pogiel, J. Rajski, Ł. Rybak, J. Tyszer, “LBIST for Automotive ICs With Enhanced Test Generation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 7, pp. 2290-2300, July 2022.
[30] G. Mrugalski, J. Rajski, J. Tyszer and B. Włodarczak, “X-Masking for In-System Deterministic Test,” in Proc. IEEE European Test Symposium (ETS), Barcelona, Spain, 2022, pp. 1-6
[31] K. -J. Lee, P. -H. Tang and M. A. Kochte, “An on-chip self-test architecture with test patterns recorded in scan chains,” in Proc. IEEE International Test Conference (ITC), Fort Worth, TX, USA, 2016, pp. 1-10.
[32] K. -J. Lee, B. -R. Chen and M. A. Kochte, “On-Chip Self-Test Methodology With All Deterministic Compressed Test Patterns Recorded in Scan Chains,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 2, pp. 309-321, Feb. 2019.
[33] J. Bush. RotorCPU [Online]. Available: https://github.com/jbush001/ RotorCPU/
[34] Parallax Propeller 1, Parallax Inc. [Online]. Available: https://www.parallax.com/propeller-1/open-source/
[35] PULP systems, PULP Platform, ETH Zurich, Institut für Integrierte Systeme, Switzerland, [Online]. Available: https://www.pulp-platform.org/
[36] OpenSPARC T2, Oracle Inc., Redwood City, CA, USA. [Online].Available:https://www.oracle.com/servers/technologies/opensparc-t2-page.html
[37] DFT Compiler, Synopsys DFT synthesis solution, https://www.synopsys.com/content/dam/synopsys/implementation&signoff/datasheets/testmax-dft-ds.pdf
[38] Design Compiler, Synopsys RTL synthesis solution, https://www.synopsys.com/implementation-and-signoff/rtl-synthesis-test/dc-ultra.html
[39] DFTMAX Ultra, Synopsys scan compression technology, https://www.synopsys.com/content/dam/synopsys/implementation%26signoff/white-papers/dftmax-ultra-wp.pdf