傳統的處理器架構主要是以指令層級平行(Instruction Level Parallelism ; ILP)來提高效能，由於程式本身固有平行程度的限制及記憶體存取延遲皆會使ILP的效能提升越來越困難，因此提升至執行緒層級平行(Thread Level Parallelism ; TLP)以隱藏ILP的平行度的限制及記憶體存取延遲。
目前TLP處理器架構設計主流基本上可分為同時多執行緒(Simultaneous Multi-thread ; SMT)及單晶片多處理器(Chip Multi-Processor ; CMP)兩種，而本論文是以CMP為設計基礎。
本論文之多執行緒計算系統架構是由處理單元(Processing Unit ; PU)、多執行緒服務單元(Multi-thread Servie Unit ; MSU)、載入及儲存單元(Load Store Unit ; LSU)及記憶體管理單元(Memory Management Unit ; MMU)四個單元所組成。
PU除了能夠同時執行多個執行緒以外，還包含執行緒的預先擷取的功能避免執行緒切換延遲，更加入了分散式同步控制器(Distribted Synchronization Controller ; DSC)來完成記憶體同步機制，以提高系統效能；執行緒間的管理主要是藉由MSU來完成，且能夠動態地將執行緒分配至PU執行，如此一來可避免藉由作業系統(軟體)來管理執行緒，增加系統執行效率；LSU能夠降低共享記憶體存取延遲以及使多個執行緒能正確的存取記憶體及避免執行緒資料錯誤；MMU內具有轉換搜尋緩衝器(Translatiion Look-aside Buffer)提供虛擬位址轉換實體位址的功能，以減少搜尋分頁對應表(Page Mapping Table ; PMT)的機會，降低記憶體存取延遲，此外還包含共享層級2指令及資料快取，提供存執行緒指令及資料存取所需。

In this dissertation, we have analysed and designed a multi-threaded computation system which is composed of a Processing Unit (PU), a Multi-thread Service Unit (MSU), a Load Store Unit (LSU) and a Memory Management Unit (MMU). The MSU contains some multi-threaded management mechanisms and is used to manage threads running efficiently. The thread processing instructions such as real-time scheduling, spawning, waiting, switching, and synchronization, are handled by MSU. Threads will be dynamically dispatched to the PU and run simultaneously. The shared L2 data cache accesses are handled by LSU, and it was designed to reduce thread stalls as much as possible. The MMU is composed of Translation Look-aside Buffers (TLB) and shared L2 instruction cache and shared L2 data cache. The TLBs are divided into Instruction TLB (ITLB) and Data TLB (DTLB) which are used for address translation from virtual address to physical address and reducing the opportunity of accessing the Page Mapping Table (PMT).

[1] D.M. Tullsen, S.J. Eggers, and H.M. Levy, “Simultaneous Multithreading: Maximizing On-Chip Parallelism,” In 22nd Annual International Symposium on Computer Architecture, June, 1995
[2] Lance Hammond, Basem A. Nayfeh, Kunle Olukotun, “A Single-Chip Multiprocessor,” IEEE Computer, September 1997, 30(9): 79-85.
[3] S. Palacharla, N. P. Jouppi, and J. E. Smith, “Quantifying the Complexity of Superscalar Processors,” University of Wisconsin-Madison, Tech. Rep. CS-1328, May 1997.
[4] J.L. Hennessy, D.A. Paterson, “Computer Architecture: A Quantitative Approach, Third Edition,” Elsevier Science Pte Ltd, 2002.
[5] William M. Johnson, “Superscalar Processor Design,” Stanford University, 1989
[6] S.J Eggers, J.S. Emer, H.M Levy, J.L. Lo, R.L. Stamm and D.M Tullsen, “Simultaneous multithreading: A platform for next-generation processors,” IEEE Micro, September 1997
[7] Lance Hammond, Benedict A. Hubbert, Michael Siu, Manohar K.Prabhu, Michael Chen, Kunle Olukotun , “The Stanford Hydra CMP,” Microprocessor, IEEE, April 2000.
[8] Jonathan Appavoo, Marc Auslander, Dilma DaSilva, David Edelsohn, Orran Krieger, Michal Ostrowski, Bryan Rosenburg, Robert W. Wisniewski, Jimi Xenidis, “K42 Overview,” IBM K42 , August 2002.
[9] Jonathan Appavoo, Marc Auslander, Dilma DaSilva, David Edelsohn, Orran Krieger, Michal Ostrowski, Bryan Rosenburg, Robert W. Wisniewski, Jimi Xenidis, “Scheduling in K42,” IBM K42, August 2001.
[10] Jonathan Appavoo, Marc Auslander, Dilma DaSilva, David Edelsohn, Orran Krieger, Michal Ostrowski, Bryan Rosenburg, Robert W. Wisniewski, Jimi Xenidis “Memory Management in K42,” IBM K42, August 2002.
[11] Adrian Tam, David Kar-Fai Tam, Reza Azimi, “Implementing Resource Containers in K42,” IBM K42, August 2002.
[12] Francisco J. Cazorla, Peter M.W. Knijnenburg, Rizos Sakellariou, Enrique Fern´andez, Alex Ramirez, Mateo Valero, “Architectural Support for Real-Time Task Scheduling in SMT Processors,” Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems, P. 166 – 176 , 2005.
[13] Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernandez, Alex Ramirez, Mateo Valero, "Implicit vs. Explicit Resource Allocation in SMT Processors," Euromicro Symposium on Digital System Design (DSD'04), pp.44-51,2004.
[14] B.D.Theelen a, A.C. Verschueren, V.V. Reyes Su_arez, M.P.J. Stevens, A.Nunez, “A scalable single-chip multi-processor architecture with on-chip RTOS kernel,” ELEVIER Journal of Systems Architecture, P.619–639, September 2003.
[15] D. W. Wall, “Limits of instruction-level parallelism,” Digital Western
Research Laboratory, Tech. Rep. 93/6, Nov. 1993.
[16] Chenjie.Yu, Peter Petrov, “Distributed and LowPower Synchronization Architecture for Embedded Multiprocessors,” Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis, P.73-78, 2008.
[17] Jenn-Yuan Tsai, Jian Huang, Christoffer Amlo, David J. Lilja, Pen-Chung Yew, “Thread Superthreaded Processor Architecture, ” IEEE TRANSACTIONS ON COMPUTERS, September 1999.
[18] J.Huang, D.J. Lilja, “An Efficient Strategy for Developing a Simulator for a Novel Concurrent Multithreaded Porcessor Architecture,” IEEE International Symposium on Modeling, July 1998.
[19] D.M. Tullsen, S.J. Eggers, and H.M. Simultaneous Multithreading: Maximizing On-Chip Parallelism, Levy, In 22nd Annual International Symposium on Computer Architecture, June, 1995
[20] S.W. Moore, B.Y. Graham, “Tagged up/down sorter – A hardware priority queue,” The Computer Journal, vol. 38, no.9, pp.695-703, Sep.1995.
[21] Saez.S, Vila.J, Crespo.A, Garcia.A, “A Hardware Scheduler for Complex Real-Time Systems,” Proceedings of the IEEE International Symposium, P.43-48, 1999.
[22] Murtaza.Z, Khan.S.A, Rafique.A, Bajwa.K.B, Zaman.U, “Silicon real time operating system for embedded DSPs,” IEEE ICET, November 2006.
[24]陳泳超, 可延展型多執行緒爪哇虛擬機器之系統晶片軟硬體協同設計, 國立成功大學電機工程學系, 碩士論文, 2007.
[23]鍾旗鴻, 同時多執行緒處理器之研究與分析, 國立成功大學電機工程學系, 碩士論文, 2010.
[25]路放, 多線程處理器體系結構模擬器的設計和實現, 中國科學技術大學計算機科學技術系, 碩士論文, 2006