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研究生: 侯人瑋
Hou, Jen-Wei
論文名稱: 應用於寬廣動態範圍電流量測之時間轉換型恆電位儀
A Time Based Potentiostat for Wide Dynamic Range Current Measurement
指導教授: 劉濱達
Liu, Bin-Da
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2015
畢業學年度: 103
語文別: 英文
論文頁數: 73
中文關鍵詞: 恆電位儀電流時間轉換器生醫感測器
外文關鍵詞: potentiostat, Current-to-Time converter, biosensor circuit
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  • 本論文提出了一個可應用於寬廣動態範圍電流量測之時間轉換型恆電位儀。文中提出了一種可藉由偵測時間輸出判斷目前量測電流範圍並自動切換到適當倍率電流鏡之電路架構,此架構可用來實現寬廣動態範圍電流量測且具備低功率消耗之特性,適合應用於設計各種不同規格之恆電位儀。此外,文中亦提供了一個有效率的設計方法配合所提出之架構去設計恆電位儀,在設計之初就能對恆電位儀晶片之各參數做取捨,如:動態電流範圍、取樣頻率、解析度、功率消耗、晶片面積等等。
    此設計以聯華電子公司0.18µm一層多晶矽六層金屬導線CMOS製程來實現,電路效能透過佈局模擬表現出126 dB (1 nA至2 mA)之動態電流範圍,最小量測電流範圍之電流解析度小於10 pA。電路之取樣頻率為1 kHz,最小功率消耗僅12 µW。電路效能足以符合各種不同生物感測器之需求。第一版晶片之量測結果與布局模擬結果相符,驗證了本論文所提設計方法與電路之可行性。

    A Time based potentiostat for wide dynamic range current measurement is presented in this thesis. We propose a circuit architecture which is well suited for designing a wide dynamic range current-to-time converter, and it is able to be used in potentiostat design for different requirements. Therefore, we provide an efficient way to make trade-offs among all the parameters, such as dynamic range, sampling frequency, resolution, power dissipation, chip area and so on.
    The proposed design is implemented in UMC 0.18-μm 1P6M CMOS technology. Circuit performance is characterized through post-layout simulation, showing a wide dynamic input current range of 126 dB (1 nA–2 mA), and the resolution at the minimum current range is smaller than 10 pA. The sampling frequency of the circuit is 1 kHz, and the minimum power dissipation is only 12 μW. Circuit performances are able to meet the requirements of different kinds of biosensors. The measurement results of the first version of the chip match with the simulation results. It demonstrates that the feasibility of the proposed method and circuit is good.

    Abstract (Chinese) i Abstract (English) iii Acknowledgement v Table of Contents vii List of Figures ix List of Tables xi Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Organization of the Thesis 4 Chapter 2 Overview of Potentiostat 5 2.1 Basic Concepts of Potentiostat 5 2.1.1 Three-electrode System 5 2.1.2 Voltammetry 6 2.1.3 Amperometry 7 2.2 Potentiostat Relative Papers 8 2.2.1 Current Mirror Based Potentiostat 9 2.2.2 Time Based Potentiostat 10 Chapter 3 The Architecture of the Proposed Circuit 15 3.1 The Proposed Time Based Potentiostat 15 3.1.1 Potential Control Loop 17 3.1.2 Current Mirror 20 3.1.3 Current-to-Time Converter with Defined Time Output Range 24 3.1.4 Logic Control Circuit for Current Range Detection 29 3.2 Design Considerations 32 3.2.1 Sampling Frequency 32 3.2.2 Dynamic Range 32 3.2.3 Power Dissipation and Other Parameters 33 3.2.4 Trade-offs among all Parameters 35 3.2.5 Variations Consideration 36 Chapter 4 Simulation and Experimental Results 37 4.1 Layout and Simulation Results 37 4.1.1 Layout of the Chip 37 4.1.2 Simulation Results 42 4.1.3 Variations 43 4.2 Experimental Results 57 4.2.1 Measurement Considerations 57 4.2.2 Measurement Environment 57 4.2.3 Measurement Results and Discussions 59 4.3 Comparison 64 Chapter 5 Conclusion 67 5.1 Conclusion 67 5.2 Future Work 68 References 69 Biography 73

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