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研究生：	蕭博群 Hsiao, Po-Chun
論文名稱：	高效能管線式類比數位轉換器及三角積分調變器之設計 Design of Power-Efficient Pipelined Analog-to-Digital Converter and Sigma-Delta Modulator
指導教授：	劉濱達 Liu, Bin-Da
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2011
畢業學年度：	99
語文別：	英文
論文頁數：	70
中文關鍵詞：	以比較器為基礎之切換電容式電路、管線式類比數位轉換器、以充電幫浦為基礎之切換電容式電路、三角積分調變器
外文關鍵詞：	comparator-based switched-capacitor circuit, pipelined ADC, charge-pump based switched-capacitor circuit, sigma-delta modulator
相關次數：	點閱：126 下載：4
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本論文提出兩種類比數位轉換器架構：一個是以比較器為基礎之管線式類比數位轉換器，另一個為以充電幫浦為基礎的三角積分調變器。
在以比較器為基礎之管線式類比數位轉換器的架構中，解決了過充電壓的問題，並提高取樣速度。其方法是將兩段式充放電改為一段式，以提高取樣速度，再搭配相關二重取樣和消除過充電壓的技巧來提高解析度。此架構使用台灣積體電路公司90 nm一層多晶矽九層金屬線製程，實現一個供應電壓1.2 V，解析度9位元，取樣頻率50 MHz的管線式類比數位轉換器。由模擬結果得知，輸入訊號頻率為1 MHz時，有效位元數為8.73位元，訊噪比為54.31 dB，FoM可達到172 fJ/轉換。
在以充電幫浦為基礎的三角積分調變器的架構中，解決了傳統以充電幫浦為基礎的切換電容式電路需要兩倍參考電壓值的問題，並且將量化器和資料加權平均演算法的動作時間延長到半個時脈周期；另外還使用低失真的架構來降低積分器的輸出擺輻。因此，使用單級運算放大器就可以達到規格要求，大幅降低功率消耗。此架構使用台灣積體電路公司90 nm一層多晶矽九層金屬線製程，實現一個供應電壓1.2 V，取樣頻率80 MHz，訊號頻寬2.5 MHz的二階，四位元量化器之三角積分調變器。由模擬結果得知，在16倍超取樣率下，有效位元數為10.894位元，訊噪比為50.52 dB，FoM可達到156.6 fJ/轉換。

In this thesis, two analog-to-digital converters are proposed: one is the comparator-based switched-capacitor (CBSC) pipelined ADC, and the other is the charge-pump based sigma-delta modulator.
In the proposed comparator-based switched-capacitor analog-to-digital structure, it only needs one charge transfer phase, and it also applies the correlated double sampling (CDS) technique and overshoot correction technique. Therefore, both the speed and the accuracy are increased. This 1.2-V, 9-bit, 50-MHz sampling frequency pipelined ADC is designed in TSMC 90-nm 1P9M CMOS process. The simulation results show that when input signal frequency is 1 MHz, the ENOB is 8.73 bits, SNDR is 54.31 dB and FoM is 172 fJ/conversion.
In the proposed charge-pump based sigma-delta-modulator, it does not need the 2VREF, and it can extend the time for quantization and DEM to half clock cycle; besides, it also uses the low distortion structure to reduce the output swing of the integrator. Therefore, we can use the single stage opamp to meet the specification of opamp, the power consumption can be greatly reduced. This 1.2-V, 80-MHz sampling frequency, 2.5-MHz signal bandwidth 2nd-order 4-bit quantizer sigma-delta modulator is design in TSMC 90-nm 1P9M CMOS process. From the simulation results, the SNDR is 50.52 dB and ENOB is 10.894 bits under the 16X OSR. The FoM is 156.6 fJ/conversion.

Abstract (Chinese)	i
Abstract (English)	ii
Acknowledgment	iv
List of figures	viii
List of tables	xii
Chapter 1 Introduction	1
1 Background and Motivation	1
2 Organization of the Thesis	2
Chapter 2 Fundamental of Analog-to-Digital Converter	3
1 Introduction of Analog-to-Digital Converter	3
2 Nyquist-Rate Converters	4
2.1 Pipelined analog-to-digital converter	5
2.2 1.5 bit/stage architecture	6
3 Oversampling Converters	8
3.1 Oversampling technique	8
3.2 Noise-shaping technique	11
4 Sigma-Delta Modulator Topologies	12
4.1 Single-loop topology	12
4.2 Multi-stage topology	15
5 Summary	16
Chapter 3 A Comparator-Based Switched-Capacitor (CBSC) Pipelined ADC with Time-Shifted Correlated Double Sampling (TSCDS) and Overshoot Correction 17
1 Introduction of Conventional CBSC Circuit	17
2 Proposed CBSC MDAC with TSCDS	19
2.1 Pseudo-differential zero-crossing-based architecture	20
2.2 Sample-and-hold (S/H) and first MDAC stage	21
2.3 Second and third MDAC stages	25
2.4 Constant TSCDS	27
3 Circuit Implementation	28
3.1 Comparator and current source	28
3.2 1.5-bit sub-ADC	29
3.3 2-bit flash ADC	30
3.4 Register and digital error correction	31
3.5 Clock generator	32
4 Simulation Results and Comparison	35
5 Layout of the CBSC pipelined ADC	38
Chapter 4 A 1.2-V, 67.3-dB SNDR, 1.49-mW 2nd-Order 4-bit Quantizer Charge-Pump Based Switched-Capacitor Sigma-Delta Modulator	39
1 Architecture Consideration	39
1.1 Design consideration	39
1.2 Feed-forward structure with relaxed DEM timing	40
2 Introduction of Charge-Pump (CP) Based Switched-Capacitor Integrator	42
3 Circuit Implementation	44
3.1 Integrator	44
3.2 Telescopic OPAMP	46
3.3 Cyclic-ADC quantizer	49
3.4 Data weighted averaging (DWA) design	53
3.5 Clock generator	56
3.6 Complete circuit diagram	58
4 Simulation Results and Layout	60
Chapter 5 Conclusions and Future Work	65
1 Conclusions	65
2 Future Work	66
References	67


                                    

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校內：2013-08-22公開
校外：2014-08-22公開

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