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研究生: 陳柏翰
Chen, Bo-Han
論文名稱: 用於高解析電視之動態適應解交錯器之架構設計與實作
Design and Implementation of Motion-adaptive Deinterlacer Architecture for High Definition TV
指導教授: 李國君
Lee, Gwo-Giun (Chris)
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2009
畢業學年度: 97
語文別: 英文
論文頁數: 84
中文關鍵詞: 高解析電視超大型積體電路動態適應解交錯器
外文關鍵詞: VLSI, deinterlacer, motion-adaptive, High definition TV
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  • 本論文介紹了演算法/架構共同設計及由上而下的設計方法並以一個已知演算法的動態適應解交錯器為例子。
    解交錯器將電視的交錯訊號轉變為循序訊號,並廣範應用於液晶顯示器 (LCD)、電漿顯示器 (plasma display)、及數位光線處理投影機(DLP projector),現今的數位電視也支援1080i (i=交錯訊號)。
    所提出架構的設計流程基於由上而下且為目標導向的設計方法,這個方法藉由將設計抽象化成多個階層,以簡化設計上的問題。為了最佳化此設計,在設計空間中探索各種設計參數的可能,包含了時脈、記憶體大小、頻寬及管線級數及其它。資料流模型是一個強大的工具,可幫助在設計空間中探索各種設計,階層式的資料流模型可用來粹取設計參數及單位資料量。論文中使用CAL的資料流導向語言能夠快速的模擬高階層的資料流。本架構最高的規格是1920x1080交錯式視訊,每秒顯示60張圖,色彩格式為4:2:2,使用tsmc.18μm製程。其所需時脈為144.9百萬赫茲,為了達到標準解析度的取樣率27百萬赫茲,其操作時脈為162百萬赫茲,其所需閘數約為137千個。

    This thesis presents a design flow of algorithm/architecture co-design, top-down design methodology and uses architecture design of deinterlacer from a given algorithm as an example.
    Deinterlacing converts interlaced signals to progressive ones, and it is well-applied in LCD displays, plasma displays, and DLP projectors. Nowadays, digital TV (DTV) also supports 1080i (i = interlaced) video sequences.
    The proposed architecture design flow is based on the concept of a “top-down” design methodology, which is a target-oriented design method. This method solves the design problem in several levels of abstractions that simplify the design problem. In order to optimize the design, design space exploration helps to explore an optimized solution in the design space including clock rate, memory size, bandwidth, pipeline depth, and so on. The dataflow model is a powerful tool that helps explore various designs in the design space. A hierarchical dataflow model is useful for extracting both the value of the design factors and the data granularity. A dataflow-oriented language called “CAL” has the advantage of modeling the high level dataflow in a short time compared with other existing language.
    The highest application is 1920x1080 interlaced video sequences with 60 fps and a color format of 4:2:2 for real time. The design technology is tsmc.18μm. The required clock rate is 144.9 MHz; however, in order to use the multiple clock rate of 27MHz (Standard Definition TV sample rate), the operation clock rate should be 162 MHz, and the gate count with line buffer should be about 137 k.

    Abstract ii Table of Contents iv List of Tables vii List of Figures ix Chapter 1 Introduction 1 1.1 Background 1 1.1.1 Interlacing and Deinterlacing 1 1.1.2 Digital TV 2 1.1.3 Design Methodology 3 1.2 Organization of this Thesis 4 Chapter 2 Overview of Deinterlacing Algorithms and Platforms 5 2.1 Problem Identification 5 2.2 Introduction to Deinterlacing Algorithms 6 2.2.1 Non-motion-compensated Deinterlacing 6 2.2.1.1 Linear method 6 2.2.1.2 Non-linear method 7 2.2.2 Motion-compensated Deinterlacing (MC) 9 2.3 Introduction to Deinterlacing platform 10 2.3.1 ASIC 10 2.3.2 Co-processor 12 2.3.3 FPGA 12 2.3.4 Others 13 2.4 Specification 13 Chapter 3 Used Algorithm 14 3.1 Used Motion Detection Algorithm 16 3.2 Used Motion Consistency Check Algorithm 20 3.3 Used Edge Detection Algorithm 22 3.4 Used Edge Consistency Check Algorithm 25 3.5 Used Interpolation Algorithm 27 Chapter 4 Architecture Design 35 4.1 Dataflow and Architecture Design 36 4.1.1 CAL model 37 4.2 Complexity Analysis & Design Space Exploration 40 4.2.1 Introduction to Complexity Analysis 40 4.2.2 Introduction to Design Space Exploration 41 4.2.3 Number of Operation 43 4.2.3.1 Edge Detection 45 4.2.3.2 Edge Consistency Check 46 4.2.3.3 Motion Detection 46 4.2.3.4 Motion Consistency Check 47 4.2.3.5 Interpolation 48 4.2.4 Degree of Parallelism 49 4.2.5 Clock Rate and Memory Usage 52 4.2.6 Pipeline Depth 60 4.2.7 Bus Bitwidth 61 4.2.8 Bandwidth 61 4.2.9 Memory Configuration 62 4.3 Exploration Result 64 4.4 Micro-Architecture 68 4.4.1 Micro-architecture of SAVTF 68 4.4.2 Micro-architecture of Edge Detection 71 Chapter 5 Experimental Result 73 5.1 Synthesis Result 73 Chapter 6 Verification 75 Chapter 7 Conclusion and future work 78 7.1 Conclusion 78 7.2 Future Work 79 Reference 80

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