成功大學博碩士論文系統

簡易檢索 / 詳目顯示

回結果列表

研究生：	王振傑 Wang, Chen-Chien
論文名稱：	雙指令集架構之嵌入式微處理器的設計與實作 Design and Implementation of a Dual-ISA Embedded Microprocessor
指導教授：	陳中和 Chen, Chung-Ho
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電腦與通信工程研究所 Institute of Computer & Communication Engineering
論文出版年：	2005
畢業學年度：	93
語文別：	中文
論文頁數：	82
中文關鍵詞：	雙指令集架構、微處理器、指令集架構、中央處理器
外文關鍵詞：	CPU, ARM, Dual-ISA, ISA, Microprocessor, MIPS
相關次數：	點閱：52 下載：3
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

　　在系統單晶片(SoC)設計中，採用不同的微處理器(microprocessor) 往往會影響到系統的整體效能，因此微處理器的選擇變成一個重要的議題。因為指令集架構(Instruction Set Architecture, ISA)特性的不同，相同的程式在不同指令集架構的微處理器上執行時，會有不同的效能表現。因此本論文提出一個雙指令集架構微處理器的平台，可以在單一微處理器核心中同時支援兩種不同的指令集架構。

　　我們選擇ARMv4/MIPS32兩種指令集為我們的實作標的，並且提出”Dual Core with Shared Resources”的實作方案。由於ARMv4指令集較MIPS32指令集複雜，因此我們首先實作一個相容於ARMv4指令集的CPU核心作為比較的基準。再根據此核心，以共用硬體資源的方式，增修原來的硬體來額外支援MIPS32的指令集。這個以ARM為出發點，整合了MIPS指令集處理能力的核心我們稱之為ARMIPS32。與原本相容於ARMv4指令集的CPU核心相比，新的ARMIPS32核心可以在同樣的時脈頻率下工作，並且只需要額外的24K個Gate就可以達到同時支援ARMv4和MIPS32的雙指令集架構。

　The Instruction Set Architecture (ISA) of a microprocessor inside a SoC system is an important design decision because the feature of the ISA dominates the overall performance of the system. It is critical to understand how efficient a program can be executed on different ISAs. In this thesis, a Dual-ISA microprocessor is proposed to accommodate the need of evaluating two different ISAs with one core.

　Two ISAs, namely ARMv4 and MIPS32 are chosen to be the implementation target of this thesis. A novel architecture called ”Dual Core with Shared Resources(DCSR)” is also proposed。A CPU core supporting ARMv4 ISA is implemented as the baseline since the ARMv4 ISA is more complex than MIPS32. Based on this CPU core, the ARMIPS32 CPU core is developed by modifying the ARM core to support MIPS32 ISA. ARMIPS32 can support ARMv4/MIPS32 Dual-ISA with only 24K extra logic gates, and retain the same clock rate of the ARM CPU Core.

CHAPTER 1  序論                                            1
1  研究動機與方向                                      1
2  研究貢獻                                            2
3  內容編排                                            2

CHAPTER 2  背景知識的介紹                                  3
1  ARM微處理器的介紹                                   3
1.1  ARMv4指令集架構                                 3
1.2  ARM的Processor Mode                             6
1.3  ARM的Register                                   6
1.4  ARM的Exception                                  8
2  MIPS微處理器的介紹                                  9
2.1  MIPS32指令集架構                               10
2.2  MIPS的Register                                 13
3  ARM與MIPS微處理器的差異                            14
3.1  Conditional Execution                          14
3.2  Conditional Branch                             15
3.3  Register File                                  15
3.4  Instruction Format and Addressing Mode         16
3.5  Load and Store Instructions                    17
3.6  Multiply Instructions                          18

CHAPTER 3  設計與實作                                     20
1  ARMV4 / MIPS32雙指令集架構微處理器的實作方案       20
1.1  MIPS Core with Binary Translation for ARMv4 ISA      21
1.2  ARM Core with Binary Translation for MIPS32 ISA      23
1.3  Dual Core with Shared Resources (DCSR)         23
2  ARMIPS32的CPU核心架構                              24
2.1  管線的控制(Pipelined Control)                  26
2.1.1  結構危障(Structural Hazard)的處理          26
2.1.2  資料危障(Data Hazard)的處理                27
2.1.3  控制危障(Control Hazard)的處理             30
2.2  資料路徑(Datapath)                             33
2.2.1  指令擷取階段(IF Stage)                     33
2.2.2  指令解碼階段(ID Stage)                     36
2.2.3  執行階段(EX Stage)                         39
2.2.4  記憶體存取階段(MEM Stage)                  41
2.2.5  資料寫回階段(WB Stage)                     43
2.3  Control Unit的設計                             44
2.4  ALU (Arithmetic Logic Unit) 的設計             46
2.5  Shifter的設計                                  47
2.6  Multiplier的設計                               48
2.7  Register Bank的設計                            53
2.8  Critical Path的改善                            54
3  ARMIPS32的MEMORY SYSTEM                            61
3.1  I-Cache的設計                                  61
3.2  D-Cache的設計                                  64
3.3  Cache Controller                               66
3.4  Bus Interface Unit (BIU)                       67
4  AMBA-BASED SOC平台                                 68
5  比較ARM9和ARMIPS32的效能與成本                     68

CHAPTER 4  模擬與驗證                                     70
1  BENCHMARKS                                         70
2  SOFTWARE VERIFICATION                              71
3  PROTOTYPING VERIFICATION                           76

CHAPTER 5  結論與未來發展                                 78
1  結論                                               78
2  未來發展                                           78
                                    

[1] ARM Corporation, http://www.arm.com
[2] ARM Corporation, “ARM Architecture Reference Manual”
[3] MIPS Corporation, http://www.mips.com
[4] MIPS Corporation, “MIPS32™ Architecture For Programmers ─ Volume I: Introduction to the MIPS32™ Architecture”
[5] MIPS Corporation, “MIPS32™ Architecture For Programmers ─ Volume II: The MIPS32™ Instruction Set”
[6] MIPS Corporation, “MIPS32™ Architecture For Programmers ─ Volume III: The MIPS32™ Privileged Resource Architecture”
[7] John L. Hennessy, and David A. Patterson, “Computer Architecture A Quantitative Approach,” 3rd edition.
[8] David A. Patterson, and John L. Hennessy, “Computer Organization and Design ─ The Hardware/Software Interface,” 3rd edition.
[9] 蔡宜穎, “A Software Design of Binary Translation System,” 碩士論文, 國立成功大學電機工程學系, 2003.
[10] 莊武憲, “Dynamic Binary Translation on a Dual-Threaded Machine,” 碩士論文, 國立成功大學電機工程學系, 2003.
[11] ARM Corporation, “ARM940T Technical Reference Manual”
[12] MIPS Corporation, “MIPS32 4Km™ Processor Core Datasheet”
[13] MIPS Corporation, “MIPS32 4K™ Processor Core Family Software User’s Manual”
[14] ARM Corporation, “AMBA Specification (Rev 2.0)”
[15] ARM Corporation, “AMBA University Kit Technical Reference Manual”
[16] Simon Segars, “The ARM9 Family – High Performance Microprocessor for Embedded Applications,” IEEE International Conference on Computer Design 1998 (ICCD’98)
[17] M. Morris Mano, “Digital Design,” 3rd edition.
[18] ModelSim, http://www.model.com
[19] ARM Corporation, “ARM Developer Suite - Version 1.2 - ADS Debug Target Guide”
[20] ARM Corporation, “ARM Developer Suite - Version 1.2 - ARM ELF Specification”
[21] ARM Corporation, “ARM Developer Suite - Version 1.2 - AXD and armsd Debuggers Guide”
[22] ARM Corporation, “ARM Developer Suite - Version 1.2 - Assembler Guide”
[23] ARM Corporation, “ARM Developer Suite - Version 1.2 - Codewarrior IDE Guide”
[24] ARM Corporation, “ARM Developer Suite - Version 1.2 - Compilers and Libraries Guide”
[25] ARM Corporation, “ARM Developer Suite - Version 1.2 - Developer Guide”
[26] ARM Corporation, “ARM Developer Suite - Version 1.2 - Getting Started”
[27] ARM Corporation, “ARM Developer Suite - Version 1.2 - Installation and License Management Guide”
[28] ARM Corporation, “ARM Developer Suite - Version 1.2 - Linker and Utilities Guide”
[29] MIPS Corporation, “MIPS® SDE 6.x Programmers’ Guide”
[30] Cygwin, http://www.cygwin.com/
[31] Altera Corporation, “Excalibur Device Overview”
[32] Altera Corporation, “EPXA10 Development Kit revision 2.1 Errata Sheet 1.4”
[33] Altera Corporation, “Excalibur EPXA10 Devices”
[34] Altera Corporation, “EPXA10 Development Board Hardware Reference Manual”
[35] Altera Corporation, “Excalibur Hardware Reference Manual”
[36] Altera Corporation, “EPXA10 Development Kit Getting Started User Guide”
[37] Altera Corporation, “Excalibur Bus Functional Model User Guide”
[38] Altera Corporation, “Excalibur Hardware Design Tutorial”
[39] Altera Corporation, “Excalibur Stripe Simulator User Guide”

校內：立即公開
校外：2005-09-06公開

簡易檢索 / 詳目顯示

相關論文