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研究生： 徐明琰
Xu, Ming-Yan
論文名稱： 應用於面板內傳輸介面之可適性等化器
Adaptive Equalizers for Intra-panel Interface
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2023
畢業學年度： 111
語文別： 英文
論文頁數： 108
中文關鍵詞： 可適性等化器 、連續時間線性之等化器 、決策回授之等化器 、計數式自適應
外文關鍵詞： adaptive equalizer, continuous-time linear equalizer (CTLE), decision feedback equalizer (DFE), counter-based adaption
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    • 本論文由兩個部分所組成，第一部分實現了一個應用於面板內傳輸介面且具有較寬輸入共模範圍的可適性等化器。此部分提出了一種連續時間線性之等化器，在1.8-V的操作電壓下，其能夠在0.3 V至1.2 V的輸入共模範圍內操作，並且不會降低高頻增益和輸入擺幅。此可適性等化器使用台積電180奈米CMOS製程進行設計與驗證，在經過1.4公尺的FR4通道，輸入資料為1.0-Gb/s和3.4-Gb/s的PRBS7訊號時，測量結果顯示抖動的峰對峰值分別為0.1 UI和0.32 UI。此次晶片的功率消耗與核心電路面積為29.4 mW 和0.185 mm^2。
    第二部分實現了一個應用於次世代8K顯示器操作於5-Gb/s之計數式可適性等化器。此部分提出了一種分析方式，從高效節能的角度來決定連續時間線性等化器的奈奎斯特頻率以及決策回授等化器的階數(number of taps)。除此之外，採用計數式自適應方法來回授調整連續時間線性等化器的補償檔位以及決策回授等化器中各階的係數。調整完畢後，採用時脈閘控的方式來關閉自適應邏輯電路的運作藉此來降低功耗。此晶片以台積電 180 奈米CMOS製程製造，其核心電路面積為 0.32 mm^2。透過布局後模擬的驗證，在通道衰減為 -22.3 dB @ 2.5 GHz 與資料速度為5-Gb/s(資料序列為 PRBS7)下，輸出峰對峰的抖動為0.04 UI。並且，在工作電壓為 1.8 V下，功率消耗為 17.8 mW，達到的能源效率為3.56 pJ/b。

    The thesis consists of two parts. The first part presents an adaptive equalizer with a wide input common mode range (ICMR) for the intra-panel interface. A continuous-time linear equalizer (CTLE) is proposed to operate with an ICMR from 0.3 V to 1.2 V under 1.8-V supply voltage without degrading the high-frequency boosting gain and input swing. The design and fabrication of this work were accomplished using the TSMC 180-nm CMOS process. The measurement results show that the peak-to-peak jitters of the equalized data are 0.1 UI and 0.32 UI at 1.0-Gb/s and 3.4-Gb/s data rate, respectively, by a PRBS7 pattern through a 1.4 meters FR4 channel. The power consumption and core area of this chip are 29.4 mW and 0.185 mm^2, respectively.
    The second part presents a 5-Gb/s counter-based adaptive equalizer for next-generation 8K displays. This part proposes a systematic analysis method to determine the Nyquist frequency of the CTLE and the number of taps in the decision feedback equalizer (DFE) for pursuing a better energy-efficiency. In addition, a counter-based adaption method is adopted to adjust the compensation gain in the CTLE and the tap coefficients in the DFE. At the end of the adjustment process, the adaption logic circuit is turned off by clock gating to reduce power consumption. The chip is fabricated in TSMC 180-nm CMOS process with a core area of 0.32 mm^2. Post-layout simulation shows that, giving a 5-Gb/s PRBS7 input data, the output peak-to-peak jitter is 0.04 UI with a channel loss of -22.3 dB at 2.5 GHz. This test chip consumes 17.8 mW under a 1.8 V supply voltage, and the energy efficiency is 3.56 pJ/b.

    摘 要 I Abstract II List of Tables IX List of Figures X Chapter 1 Introduction 1 1.1 Background 1 1.2 Motivation 5 1.3 Thesis Organization 6 Chapter 2 Background Knowledge of Wireline Communication System 7 2.1 Overview of Wireline Communication System 7 2.2 Pseudo-Random Binary Sequence 9 2.3 Data Formats 10 2.4 Channel Characteristics 12 2.5 Jitter 14 2.5.1 The Definition of Jitter 14 2.5.2 The Composition of Jitter 15 2.6 Eye Diagram 17 Chapter 3 Adaptive Equalizer 19 3.1 Introduction to Equalizer 20 3.1.1 The Continuous-time Linear Equalizer 21 3.1.2 The Decision Feedback Equalizer 23 3.1.3 The Hybrid Equalizer 25 3.2 Design Techniques of Continuous-time Linear Equalizer 26 3.2.1 Inductive Peaking Technique [17] 26 3.2.2 Negative Capacitance Technique [18] 27 3.3 Design Techniques of Decision Feedback Equalizer 28 3.3.1 Look-ahead DFE [19] 29 3.3.2 Infinite Impulse Response DFE [20] 30 3.3.3 Current-integrating DFE [21] 31 3.4 Design Techniques of Adaption Circuit 33 3.4.1 Prior Works for CTLE 34 3.4.2 Prior Works for DFE 38 3.4.3 Prior Works for Hybrid Equalizer 41 Chapter 4 A 1.0- to 3.4-Gb/s Adaptive CTLE with the wide ICMR for Intra-panel Interface 47 4.1 Introduction 47 4.2 Proposed Adaptive CTLE with Wide ICMR 49 4.2.1 Architecture of the Proposed Adaptive CTLE 50 4.2.2 Proposed CTLE with Wide ICMR 51 4.3 Circuit Description 54 4.3.1 Slicer 54 4.3.2 Bandpass Filter (BPF) 55 4.3.3 Rectifier 56 4.3.4 Error Amplifier 57 4.3.5 Layout and Chip Floor Plan 58 4.4 Experiment Result 60 4.4.1 Simulation Results 60 4.4.2 Chip Micrograph and Measurement Setup 67 4.4.3 Measurement Results 70 4.4.4 Comparison Table 74 Chapter 5 A 1.0- to 5.0-Gb/s Counter-based Adaptive CTLE and DFE for Next-Generation 8K Displays 75 5.1 Introduction 75 5.2 Proposed Analysis for Parameter Allocation of CTLE and DFE 76 5.3 Circuit Description 85 5.3.1 Architecture 85 5.3.2 2-stage CTLE 87 5.3.3 2-tap direct DFE 88 5.3.4 Counter-based Adaption 90 5.3.5 Clock Multiplexer 92 5.3.6 Layout and Floor Plan 93 5.4 Experiment Result 95 5.4.1 Simulation Results 95 5.4.2 Comparison Table 100 Chapter 6 Conclusion and Future Work 101 6.1 Conclusion 101 6.2 Future Work 102 Bibliography 103

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