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研究生： 黃聖文
Huang, Sheng-Wen
論文名稱： 一個基於二元搜尋樹的回切技巧與殘值超取樣架構的十四位元每秒取樣二百萬次之逐漸趨近式類比數位轉換器
A 14-bit 2-MS/s Successive-Approximation Analog-to-Digital Converter with Tree-Based Reversed Switching and Residue Oversampling
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2020
畢業學年度： 108
語文別： 英文
論文頁數： 108
中文關鍵詞： 逐漸趨近式類比數位轉換器 、高線性 、高解析 、超取樣 、殘值超取樣
外文關鍵詞： Successive-approximation register (SAR) analog-to-digital converter (ADC), High-linearity, High-resolution, Oversampling, Residue Oversampling
相關次數： 點閱：171  下載：32 
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    • 本論文提出一個高線性與高解析度之十四位元每秒取樣二百萬次逐漸趨近式類比數位轉換器。
    此晶片結合了殘值超取樣的架構與本論文所提出的基於二元搜尋樹之回切技巧。所提出之回切技巧能透過重複利用已經切換過的電容進行回切來避免新的電容切換，減少電容不匹配的影響。而殘值超取樣技術透過交換電容的排列方式，產生不同的殘值電壓，對同一次取樣的殘值電壓做多次的量化，來產生較精確的數位碼。結合以上兩種技術，在不需校正的技巧下，能提升類比數位轉換器的精確度與有效減少電容不匹配的影響。
    本論文以台積電180奈米製程研製一個十四位元的逐漸趨近式類比數位轉換器，核心電路面積為1.246mm2。當晶片操作在1.8伏特的電壓供應下與200萬赫茲(2-MS/s)的取樣頻率時，實測效能顯示，在奈奎斯特(Nyquist-rate)輸入頻率下，可以達到有效位元為 12.05 位元(SNDR為 74.28 dB)，換算得到的轉換效率為 165.77 dB。

    This thesis presents a high-linearity and high-resolution, 14-bit 2-MS/s successive-approximation register (SAR) analog-to-digital converter (ADC).
    This chip adopts proposed Tree-Based Reversed Switching and Residue Oversampling. With the proposed Tree-Based Reversed Switching, switched capacitors could be reused to avoid new capacitor switching. Therefore, influence of capacitor mismatch is reduced. For Residue Oversampling, roles of capacitors are rearranged to generate different residue voltages, and residue voltages of the same sample are quantized and averaged to generate a high-precision digital code. By combining these two techniques, the accuracy of the ADC is improved and capacitor mismatch is reduced without calibration techniques.
    The proof-of-concept 14-bit SAR ADC was fabricated in a TSMC 180-nm CMOS technology, of which the core circuits occupy an area of 1.246mm2. As the prototype operates at a supply voltage of 1.8-V and sampling rate of 2-MS/s, the measurement results show that the prototype ADC achieves 74.28 dB SNDR with a Nyquist-rate input. The Figure of Merit (FoMs) is 165.77 dB.

    摘　要---I Abstract---II List of Tables---VII List of Figures---VIII List of Abbreviations---XIII Chapter1 Introduction---1 1.1 Background and Motivation---1 1.2 Thesis Organization---4 Chapter2 Fundamentals of Analog-to-Digital Converters---5 2.1 Analog to Digital Converter---5 2.2 Quantization Error---6 2.3 Resolution and Accuracy---7 2.4 Static Specification---8 2.4.1 Offset Error---8 2.4.2 Gain Error---9 2.4.3 Nonlinearity---10 2.5 Dynamic Specification---15 2.5.1 Signal-to-Noise Ratio (SNR)---15 2.5.2 Signal-to-Noise and Distortion Ratio (SNDR)---16 2.5.3 Effective Number of Bits (ENOB)---17 2.5.4 Spurious-Free Dynamic Range (SFDR)---17 2.5.5 Total Harmonic Distortion (THD)---18 2.5.6 Effective Resolution Bandwidth (ERBW)---19 2.5.7 Figure of Merit (FoM)---20 Chapter3 High-Resolution SAR ADC---21 3.1 The Basic of SAR ADC---21 3.1.1 The Concept of SAR ADC---22 3.1.2 Circuit Operation of the SAR ADC Architecture---23 3.1.3 Performance Limitations of High-Resolution SAR ADCs---25 3.2 Oversampling---29 3.3 Techniques for Nyquist-Rate ADCs---32 3.3.1 Correlated-Reversed Switching Technique---32 3.3.2 Detect-and-Skip Algorithm---33 3.3.3 Majority-Voting Technique---35 3.3.4 Adaptive-Averaging Technique---36 3.3.5 Pipelined SAR ADC---37 Chapter4 A 14-bit 2-MS/s SAR ADC---40 4.1 Techniques Adopted---41 4.1.1 Tree-Based Reversed Switching---41 4.1.2 Residue Oversampling---52 4.2 Architecture of the proposed SAR ADC---57 4.2.1 Simplified-DEM Structure---58 4.2.2 Error-Tolerance Range---59 4.2.3 Architecture---61 4.2.4 Capacitor Switching Methods---63 4.3 Behavior Model Simulations---67 4.3.1 Behavior Model Simulations with Capacitor Mismatch---67 4.3.2 Behavior Model Simulations with Noise---70 4.4 Circuit Implementation---71 4.4.1 Bootstrapped Switch---71 4.4.2 Dynamic Two-Stage Comparator---73 4.4.3 Tree-Based Reversed Switching Implementation---76 4.4.4 Digital Error Correction Decoder---79 4.4.5 Capacitive DAC---81 Chapter5 Simulation and Measurement Results---84 5.1 Layout and Chip Floor Plan---84 5.2 Simulation Results---87 5.3 PCB Design Consideration---91 5.4 Micrograph and Measurement Setup---92 5.5 Measurement Results---94 Chapter6 Conclusions and Future Works---102 Bibliography---104

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