半導體製造技術的進步促使單晶片系統設計可整合更多複雜的核心電路以及提升系統的操作頻率，但卻使得延遲錯誤之測試流程變得更加地複雜。在本篇論文中，為了能夠有效地執行延遲錯誤的測試流程，我們提出一內嵌式延遲錯誤測試的架構以針對包覆IEEE 1500標準介面且擁有多時脈域的核心電路進行測試。針對延遲測試所需的控制訊號以及時脈皆可由我們所提出的晶片系統延遲測試架構所產生，如此則可減低對外部測試機台的需求以大幅降低測試的成本。延遲測試的架構由一內嵌於IEEE 1500介面的延遲時脈產生器所組成，搭配相位鎖定迴路電路提供的參考時脈以達到精準的時脈控制。此架構針對延遲測試提供觸發後擷取(launch off capture, LOC)方法且能夠針對在電路內或電路之間支援單一時脈域或多重時脈域的延遲測試。任何電路包覆我們所設計的支援延遲測試的IEEE 1500介面可以更方便且快速地整合至延遲測試架構以達到隨插即用的功能。根據本實驗結果顯示，我們提出的延遲測試架構針對單一時脈域或是多重時脈域確實皆可有效的執行延遲測試。

High-performance system-on-a-chip (SOC) designs nowadays are usually implemented using multiple clocks. This, however, also complicates test procedures for timing-related defects (usually modeled as delay faults) in the chip. This thesis presents an on-chip delay test architecture based on the IEEE 1500 standard for multi-clock core-based SOC designs to cost-effectively carry out delay test procedures. All required test control signals and at-speed clocks for delay test can be generated on-chip so that the need of external automatic test equipment (ATE) to provide these signals can be eliminated and test costs can be greatly reduced. To achieve high quality of delay tests, the delay test architecture including basic SOC components, the SOC test platform [1], and the IEEE 1500 standard compliant wrapper design equipped with a novel delay test clock generator is presented to support core-based delay tests of intra-clock domains and inter-clock domains within a core or between cores. Any core wrapped by the proposed wrapper can be easily integrated to our test architecture in a plug-and-play manner. Experimental results show the effectiveness of the proposed on-chip delay test architecture for multi-clock domains delay test.

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